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bac89f3dd2
llvm-6502/test/CodeGen
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Tom Stellard bac89f3dd2 R600/SI: Insert s_waitcnt before s_barrier instructions. 
This ensures that all memory operations are complete when all threads
reach the barrier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225290 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 19:52:07 +00:00
..
AArch64 [AArch64] Improve codegen of store lane instructions by avoiding GPR usage. 2015-01-05 17:10:26 +00:00
ARM Emit the build attribute Tag_conformance. 2015-01-05 13:12:17 +00:00
CPP
Generic CodeGen: do not attempt to invalidate virtual registers for zero-sized phis. 2014-12-19 20:50:07 +00:00
Hexagon [Hexagon] Adding dealloc_return encoding and absolute address stores. 2015-01-06 16:15:15 +00:00
Inputs IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Mips [mips][microMIPS] Fix bugs related to atomic SC/LL instructions 2014-12-18 16:39:29 +00:00
MSP430
NVPTX [NVPTX] Fix bugs related to isSingleValueType 2014-12-17 17:59:04 +00:00
PowerPC [PowerPC] Add a regression test for r225251 2015-01-06 16:46:37 +00:00
R600 R600/SI: Insert s_waitcnt before s_barrier instructions. 2015-01-06 19:52:07 +00:00
SPARC IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
SystemZ IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Thumb IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Thumb2 IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
X86 [CodeGenPrepare] Improved logic to speculate calls to cttz/ctlz. 2015-01-06 17:41:18 +00:00
XCore IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00