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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203220 91177308-0d34-0410-b5e6-96231b3b80d8
281 lines
11 KiB
C++
281 lines
11 KiB
C++
//==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ScheduleDAGInstrs class, which implements
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// scheduling for a MachineInstr-based dependency graph.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
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#define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
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#include "llvm/ADT/SparseMultiSet.h"
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#include "llvm/ADT/SparseSet.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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namespace llvm {
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class MachineFrameInfo;
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class MachineLoopInfo;
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class MachineDominatorTree;
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class LiveIntervals;
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class RegPressureTracker;
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class PressureDiffs;
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/// An individual mapping from virtual register number to SUnit.
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struct VReg2SUnit {
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unsigned VirtReg;
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SUnit *SU;
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VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
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unsigned getSparseSetIndex() const {
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return TargetRegisterInfo::virtReg2Index(VirtReg);
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}
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};
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/// Record a physical register access.
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/// For non-data-dependent uses, OpIdx == -1.
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struct PhysRegSUOper {
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SUnit *SU;
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int OpIdx;
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unsigned Reg;
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PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
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unsigned getSparseSetIndex() const { return Reg; }
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};
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/// Use a SparseMultiSet to track physical registers. Storage is only
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/// allocated once for the pass. It can be cleared in constant time and reused
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/// without any frees.
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typedef SparseMultiSet<PhysRegSUOper, llvm::identity<unsigned>, uint16_t>
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Reg2SUnitsMap;
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/// Use SparseSet as a SparseMap by relying on the fact that it never
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/// compares ValueT's, only unsigned keys. This allows the set to be cleared
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/// between scheduling regions in constant time as long as ValueT does not
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/// require a destructor.
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typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;
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/// Track local uses of virtual registers. These uses are gathered by the DAG
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/// builder and may be consulted by the scheduler to avoid iterating an entire
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/// vreg use list.
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typedef SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2UseMap;
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/// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
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/// MachineInstrs.
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class ScheduleDAGInstrs : public ScheduleDAG {
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protected:
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const MachineLoopInfo &MLI;
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const MachineDominatorTree &MDT;
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const MachineFrameInfo *MFI;
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/// Live Intervals provides reaching defs in preRA scheduling.
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LiveIntervals *LIS;
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/// TargetSchedModel provides an interface to the machine model.
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TargetSchedModel SchedModel;
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/// isPostRA flag indicates vregs cannot be present.
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bool IsPostRA;
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/// True if the DAG builder should remove kill flags (in preparation for
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/// rescheduling).
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bool RemoveKillFlags;
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/// The standard DAG builder does not normally include terminators as DAG
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/// nodes because it does not create the necessary dependencies to prevent
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/// reordering. A specialized scheduler can override
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/// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
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/// it has taken responsibility for scheduling the terminator correctly.
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bool CanHandleTerminators;
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/// State specific to the current scheduling region.
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/// ------------------------------------------------
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/// The block in which to insert instructions
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MachineBasicBlock *BB;
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/// The beginning of the range to be scheduled.
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MachineBasicBlock::iterator RegionBegin;
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/// The end of the range to be scheduled.
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MachineBasicBlock::iterator RegionEnd;
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/// Instructions in this region (distance(RegionBegin, RegionEnd)).
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unsigned NumRegionInstrs;
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/// After calling BuildSchedGraph, each machine instruction in the current
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/// scheduling region is mapped to an SUnit.
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DenseMap<MachineInstr*, SUnit*> MISUnitMap;
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/// After calling BuildSchedGraph, each vreg used in the scheduling region
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/// is mapped to a set of SUnits. These include all local vreg uses, not
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/// just the uses for a singly defined vreg.
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VReg2UseMap VRegUses;
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/// State internal to DAG building.
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/// -------------------------------
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/// Defs, Uses - Remember where defs and uses of each register are as we
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/// iterate upward through the instructions. This is allocated here instead
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/// of inside BuildSchedGraph to avoid the need for it to be initialized and
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/// destructed for each block.
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Reg2SUnitsMap Defs;
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Reg2SUnitsMap Uses;
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/// Track the last instruction in this region defining each virtual register.
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VReg2SUnitMap VRegDefs;
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/// PendingLoads - Remember where unknown loads are after the most recent
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/// unknown store, as we iterate. As with Defs and Uses, this is here
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/// to minimize construction/destruction.
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std::vector<SUnit *> PendingLoads;
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/// DbgValues - Remember instruction that precedes DBG_VALUE.
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/// These are generated by buildSchedGraph but persist so they can be
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/// referenced when emitting the final schedule.
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typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
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DbgValueVector;
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DbgValueVector DbgValues;
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MachineInstr *FirstDbgValue;
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/// Set of live physical registers for updating kill flags.
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BitVector LiveRegs;
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public:
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explicit ScheduleDAGInstrs(MachineFunction &mf,
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const MachineLoopInfo &mli,
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const MachineDominatorTree &mdt,
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bool IsPostRAFlag,
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bool RemoveKillFlags = false,
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LiveIntervals *LIS = 0);
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virtual ~ScheduleDAGInstrs() {}
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bool isPostRA() const { return IsPostRA; }
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/// \brief Expose LiveIntervals for use in DAG mutators and such.
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LiveIntervals *getLIS() const { return LIS; }
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/// \brief Get the machine model for instruction scheduling.
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const TargetSchedModel *getSchedModel() const { return &SchedModel; }
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/// \brief Resolve and cache a resolved scheduling class for an SUnit.
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const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
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if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
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SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
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return SU->SchedClass;
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}
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/// begin - Return an iterator to the top of the current scheduling region.
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MachineBasicBlock::iterator begin() const { return RegionBegin; }
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/// end - Return an iterator to the bottom of the current scheduling region.
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MachineBasicBlock::iterator end() const { return RegionEnd; }
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/// newSUnit - Creates a new SUnit and return a ptr to it.
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SUnit *newSUnit(MachineInstr *MI);
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/// getSUnit - Return an existing SUnit for this MI, or NULL.
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SUnit *getSUnit(MachineInstr *MI) const;
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/// startBlock - Prepare to perform scheduling in the given block.
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virtual void startBlock(MachineBasicBlock *BB);
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/// finishBlock - Clean up after scheduling in the given block.
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virtual void finishBlock();
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/// Initialize the scheduler state for the next scheduling region.
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virtual void enterRegion(MachineBasicBlock *bb,
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MachineBasicBlock::iterator begin,
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MachineBasicBlock::iterator end,
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unsigned regioninstrs);
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/// Notify that the scheduler has finished scheduling the current region.
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virtual void exitRegion();
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/// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are
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/// input.
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void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker = 0,
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PressureDiffs *PDiffs = 0);
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/// addSchedBarrierDeps - Add dependencies from instructions in the current
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/// list of instructions being scheduled to scheduling barrier. We want to
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/// make sure instructions which define registers that are either used by
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/// the terminator or are live-out are properly scheduled. This is
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/// especially important when the definition latency of the return value(s)
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/// are too high to be hidden by the branch or when the liveout registers
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/// used by instructions in the fallthrough block.
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void addSchedBarrierDeps();
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/// schedule - Order nodes according to selected style, filling
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/// in the Sequence member.
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///
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/// Typically, a scheduling algorithm will implement schedule() without
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/// overriding enterRegion() or exitRegion().
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virtual void schedule() = 0;
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/// finalizeSchedule - Allow targets to perform final scheduling actions at
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/// the level of the whole MachineFunction. By default does nothing.
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virtual void finalizeSchedule() {}
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void dumpNode(const SUnit *SU) const override;
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/// Return a label for a DAG node that points to an instruction.
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std::string getGraphNodeLabel(const SUnit *SU) const override;
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/// Return a label for the region of code covered by the DAG.
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std::string getDAGName() const override;
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/// \brief Fix register kill flags that scheduling has made invalid.
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void fixupKills(MachineBasicBlock *MBB);
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protected:
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void initSUnits();
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void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
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void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
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void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
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void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
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/// \brief PostRA helper for rewriting kill flags.
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void startBlockForKills(MachineBasicBlock *BB);
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/// \brief Toggle a register operand kill flag.
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///
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/// Other adjustments may be made to the instruction if necessary. Return
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/// true if the operand has been deleted, false if not.
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bool toggleKillFlag(MachineInstr *MI, MachineOperand &MO);
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};
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/// newSUnit - Creates a new SUnit and return a ptr to it.
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inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
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#ifndef NDEBUG
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const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
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#endif
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SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
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assert((Addr == 0 || Addr == &SUnits[0]) &&
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"SUnits std::vector reallocated on the fly!");
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SUnits.back().OrigNode = &SUnits.back();
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return &SUnits.back();
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}
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/// getSUnit - Return an existing SUnit for this MI, or NULL.
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inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
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DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
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if (I == MISUnitMap.end())
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return 0;
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return I->second;
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}
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} // namespace llvm
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#endif
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