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AArch64
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Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
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2013-09-04 09:28:24 +00:00 |
ARM
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Swift: Only build vldm/vstm with q register aligned register lists
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2013-09-04 17:41:16 +00:00 |
CPP
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[tests] Cleanup initialization of test suffixes.
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2013-08-16 00:37:11 +00:00 |
Generic
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[tests] Cleanup initialization of test suffixes.
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2013-08-16 00:37:11 +00:00 |
Hexagon
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Debug Info: add an identifier field to DICompositeType.
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2013-08-26 22:39:55 +00:00 |
Inputs
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Debug Info: add an identifier field to DICompositeType.
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2013-08-26 22:39:55 +00:00 |
Mips
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Make sure we don't generate stubs for any of these functions because they
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2013-09-01 04:12:59 +00:00 |
MSP430
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[tests] Cleanup initialization of test suffixes.
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2013-08-16 00:37:11 +00:00 |
NVPTX
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[NVPTX] Re-enable assembly printing support for inline assembly
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2013-08-24 01:17:23 +00:00 |
PowerPC
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[PowerPC] Call support for fast-isel.
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2013-08-30 22:18:55 +00:00 |
R600
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R600: Non vector only instruction can be scheduled on trans unit
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2013-09-04 19:53:46 +00:00 |
SPARC
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[Sparc] Fix an assertion failure while lowering fcmp on long double.
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2013-09-04 15:15:20 +00:00 |
SystemZ
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[SystemZ] Add support for TMHH, TMHL, TMLH and TMLL
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2013-09-03 15:38:35 +00:00 |
Thumb
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ARM: Use "dmb sy" for barriers on M-class CPUs
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2013-08-28 14:39:19 +00:00 |
Thumb2
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ARM: make sure ARM-mode pseudo-inst requires IsARM
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2013-08-23 10:16:39 +00:00 |
X86
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FileCheck-ize three tests of llvm/test/CodeGen/X86/h-register(s).
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2013-09-02 12:00:53 +00:00 |
XCore
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[tests] Cleanup initialization of test suffixes.
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2013-08-16 00:37:11 +00:00 |