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on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
626 lines
23 KiB
C++
626 lines
23 KiB
C++
//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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#include "PPCRegisterInfo.h"
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#include "PPC.h"
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#include "PPCInstrBuilder.h"
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#include "PPCMachineFunctionInfo.h"
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#include "PPCFrameLowering.h"
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#include "PPCSubtarget.h"
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#include "llvm/CallingConv.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include <cstdlib>
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#define GET_REGINFO_TARGET_DESC
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#include "PPCGenRegisterInfo.inc"
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namespace llvm {
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cl::opt<bool> DisablePPC32RS("disable-ppc32-regscavenger",
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cl::init(false),
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cl::desc("Disable PPC32 register scavenger"),
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cl::Hidden);
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cl::opt<bool> DisablePPC64RS("disable-ppc64-regscavenger",
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cl::init(false),
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cl::desc("Disable PPC64 register scavenger"),
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cl::Hidden);
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}
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using namespace llvm;
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// FIXME (64-bit): Should be inlined.
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bool
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PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
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return ((!DisablePPC32RS && !Subtarget.isPPC64()) ||
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(!DisablePPC64RS && Subtarget.isPPC64()));
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}
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PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
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const TargetInstrInfo &tii)
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: PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
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ST.isPPC64() ? 0 : 1,
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ST.isPPC64() ? 0 : 1),
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Subtarget(ST), TII(tii) {
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
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ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
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ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
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ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
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ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
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// 64-bit
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ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
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ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
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ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
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ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
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ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
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}
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bool
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PPCRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
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return requiresRegisterScavenging(MF);
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}
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *
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PPCRegisterInfo::getPointerRegClass(unsigned Kind) const {
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if (Subtarget.isPPC64())
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return &PPC::G8RCRegClass;
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return &PPC::GPRCRegClass;
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}
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const uint16_t*
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PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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if (Subtarget.isDarwinABI())
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return Subtarget.isPPC64() ? CSR_Darwin64_SaveList :
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CSR_Darwin32_SaveList;
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return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList;
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}
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const unsigned*
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PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
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if (Subtarget.isDarwinABI())
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return Subtarget.isPPC64() ? CSR_Darwin64_RegMask :
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CSR_Darwin32_RegMask;
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return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask;
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}
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BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const PPCFrameLowering *PPCFI =
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static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
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Reserved.set(PPC::R0);
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Reserved.set(PPC::R1);
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Reserved.set(PPC::LR);
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Reserved.set(PPC::LR8);
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Reserved.set(PPC::RM);
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// The SVR4 ABI reserves r2 and r13
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if (Subtarget.isSVR4ABI()) {
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Reserved.set(PPC::R2); // System-reserved register
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Reserved.set(PPC::R13); // Small Data Area pointer register
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}
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// Reserve R2 on Darwin to hack around the problem of save/restore of CR
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// when the stack frame is too big to address directly; we need two regs.
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// This is a hack.
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if (Subtarget.isDarwinABI()) {
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Reserved.set(PPC::R2);
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}
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// On PPC64, r13 is the thread pointer. Never allocate this register.
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// Note that this is over conservative, as it also prevents allocation of R31
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// when the FP is not needed.
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if (Subtarget.isPPC64()) {
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Reserved.set(PPC::R13);
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Reserved.set(PPC::R31);
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Reserved.set(PPC::X0);
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Reserved.set(PPC::X1);
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Reserved.set(PPC::X13);
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Reserved.set(PPC::X31);
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// The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
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if (Subtarget.isSVR4ABI()) {
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Reserved.set(PPC::X2);
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}
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// Reserve X2 on Darwin to hack around the problem of save/restore of CR
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// when the stack frame is too big to address directly; we need two regs.
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// This is a hack.
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if (Subtarget.isDarwinABI()) {
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Reserved.set(PPC::X2);
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}
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}
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if (PPCFI->needsFP(MF))
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Reserved.set(PPC::R31);
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return Reserved;
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}
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unsigned
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PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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const unsigned DefaultSafety = 1;
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switch (RC->getID()) {
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default:
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return 0;
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case PPC::G8RCRegClassID:
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case PPC::GPRCRegClassID: {
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unsigned FP = TFI->hasFP(MF) ? 1 : 0;
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return 32 - FP - DefaultSafety;
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}
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case PPC::F8RCRegClassID:
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case PPC::F4RCRegClassID:
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case PPC::VRRCRegClassID:
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return 32 - DefaultSafety;
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case PPC::CRRCRegClassID:
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return 8 - DefaultSafety;
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}
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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void PPCRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (MF.getTarget().Options.GuaranteedTailCallOpt &&
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I->getOpcode() == PPC::ADJCALLSTACKUP) {
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// Add (actually subtract) back the amount the callee popped on return.
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if (int CalleeAmt = I->getOperand(1).getImm()) {
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bool is64Bit = Subtarget.isPPC64();
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CalleeAmt *= -1;
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unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
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unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
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unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
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unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
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unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
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unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
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MachineInstr *MI = I;
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DebugLoc dl = MI->getDebugLoc();
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if (isInt<16>(CalleeAmt)) {
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BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
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.addReg(StackReg, RegState::Kill)
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.addImm(CalleeAmt);
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} else {
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MachineBasicBlock::iterator MBBI = I;
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BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
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.addImm(CalleeAmt >> 16);
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BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
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.addReg(TmpReg, RegState::Kill)
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.addImm(CalleeAmt & 0xFFFF);
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BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
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.addReg(StackReg, RegState::Kill)
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.addReg(TmpReg);
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}
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}
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}
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// Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
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MBB.erase(I);
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}
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/// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
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/// register first and then a spilled callee-saved register if that fails.
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static
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unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
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const TargetRegisterClass *RC, int SPAdj) {
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assert(RS && "Register scavenging must be on");
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unsigned Reg = RS->FindUnusedReg(RC);
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// FIXME: move ARM callee-saved reg scan to target independent code, then
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// search for already spilled CS register here.
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if (Reg == 0)
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Reg = RS->scavengeRegister(RC, II, SPAdj);
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return Reg;
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}
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/// lowerDynamicAlloc - Generate the code for allocating an object in the
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/// current frame. The sequence of code with be in the general form
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///
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/// addi R0, SP, \#frameSize ; get the address of the previous frame
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/// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
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/// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
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///
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void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS) const {
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// Get the instruction.
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MachineInstr &MI = *II;
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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// Get the basic block's function.
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MachineFunction &MF = *MBB.getParent();
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// Get the frame info.
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Determine whether 64-bit pointers are used.
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bool LP64 = Subtarget.isPPC64();
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DebugLoc dl = MI.getDebugLoc();
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// Get the maximum call stack size.
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unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
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// Get the total frame size.
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unsigned FrameSize = MFI->getStackSize();
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// Get stack alignments.
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unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
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unsigned MaxAlign = MFI->getMaxAlignment();
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if (MaxAlign > TargetAlign)
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report_fatal_error("Dynamic alloca with large aligns not supported");
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// Determine the previous frame's address. If FrameSize can't be
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// represented as 16 bits or we need special alignment, then we load the
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// previous frame's address from 0(SP). Why not do an addis of the hi?
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// Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
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// Constructing the constant and adding would take 3 instructions.
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// Fortunately, a frame greater than 32K is rare.
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const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
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// FIXME (64-bit): Use "findScratchRegister"
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unsigned Reg;
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if (requiresRegisterScavenging(MF))
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Reg = findScratchRegister(II, RS, RC, SPAdj);
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else
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Reg = PPC::R0;
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if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
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BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
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.addReg(PPC::R31)
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.addImm(FrameSize);
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} else if (LP64) {
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if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
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BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
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.addImm(0)
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.addReg(PPC::X1);
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else
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BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
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.addImm(0)
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.addReg(PPC::X1);
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} else {
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BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
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.addImm(0)
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.addReg(PPC::R1);
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}
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// Grow the stack and update the stack pointer link, then determine the
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// address of new allocated space.
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if (LP64) {
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if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
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BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
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.addReg(Reg, RegState::Kill)
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.addReg(PPC::X1, RegState::Define)
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.addReg(MI.getOperand(1).getReg());
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else
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BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
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.addReg(PPC::X0, RegState::Kill)
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.addReg(PPC::X1, RegState::Define)
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.addReg(MI.getOperand(1).getReg());
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if (!MI.getOperand(1).isKill())
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BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
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.addReg(PPC::X1)
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.addImm(maxCallFrameSize);
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else
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// Implicitly kill the register.
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BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
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.addReg(PPC::X1)
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.addImm(maxCallFrameSize)
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.addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
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} else {
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BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
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.addReg(Reg, RegState::Kill)
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.addReg(PPC::R1, RegState::Define)
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.addReg(MI.getOperand(1).getReg());
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if (!MI.getOperand(1).isKill())
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BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
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.addReg(PPC::R1)
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.addImm(maxCallFrameSize);
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else
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// Implicitly kill the register.
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BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
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.addReg(PPC::R1)
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.addImm(maxCallFrameSize)
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.addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
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}
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// Discard the DYNALLOC instruction.
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MBB.erase(II);
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}
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/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
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/// reserving a whole register (R0), we scrounge for one here. This generates
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/// code like this:
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///
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/// mfcr rA ; Move the conditional register into GPR rA.
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/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
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/// stw rA, FI ; Store rA to the frame.
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///
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void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
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unsigned FrameIndex, int SPAdj,
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RegScavenger *RS) const {
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// Get the instruction.
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MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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// FIXME: Once LLVM supports creating virtual registers here, or the register
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// scavenger can return multiple registers, stop using reserved registers
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// here.
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(void) SPAdj;
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(void) RS;
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bool LP64 = Subtarget.isPPC64();
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unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) :
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(LP64 ? PPC::X0 : PPC::R0);
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unsigned SrcReg = MI.getOperand(0).getReg();
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// We need to store the CR in the low 4-bits of the saved value. First, issue
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// an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg)
|
|
.addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
|
|
|
|
// If the saved register wasn't CR0, shift the bits left so that they are in
|
|
// CR0's slot.
|
|
if (SrcReg != PPC::CR0)
|
|
// rlwinm rA, rA, ShiftBits, 0, 31.
|
|
BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
|
|
.addReg(Reg, RegState::Kill)
|
|
.addImm(getPPCRegisterNumbering(SrcReg) * 4)
|
|
.addImm(0)
|
|
.addImm(31);
|
|
|
|
addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
|
|
.addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
|
|
FrameIndex);
|
|
|
|
// Discard the pseudo instruction.
|
|
MBB.erase(II);
|
|
}
|
|
|
|
void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
|
|
unsigned FrameIndex, int SPAdj,
|
|
RegScavenger *RS) const {
|
|
// Get the instruction.
|
|
MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
|
|
// Get the instruction's basic block.
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
DebugLoc dl = MI.getDebugLoc();
|
|
|
|
// FIXME: Once LLVM supports creating virtual registers here, or the register
|
|
// scavenger can return multiple registers, stop using reserved registers
|
|
// here.
|
|
(void) SPAdj;
|
|
(void) RS;
|
|
|
|
bool LP64 = Subtarget.isPPC64();
|
|
unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) :
|
|
(LP64 ? PPC::X0 : PPC::R0);
|
|
unsigned DestReg = MI.getOperand(0).getReg();
|
|
assert(MI.definesRegister(DestReg) &&
|
|
"RESTORE_CR does not define its destination");
|
|
|
|
addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
|
|
Reg), FrameIndex);
|
|
|
|
// If the reloaded register isn't CR0, shift the bits right so that they are
|
|
// in the right CR's slot.
|
|
if (DestReg != PPC::CR0) {
|
|
unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
|
|
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
|
|
BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
|
|
.addReg(Reg).addImm(32-ShiftBits).addImm(0)
|
|
.addImm(31);
|
|
}
|
|
|
|
BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
|
|
.addReg(Reg);
|
|
|
|
// Discard the pseudo instruction.
|
|
MBB.erase(II);
|
|
}
|
|
|
|
void
|
|
PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
int SPAdj, RegScavenger *RS) const {
|
|
assert(SPAdj == 0 && "Unexpected");
|
|
|
|
// Get the instruction.
|
|
MachineInstr &MI = *II;
|
|
// Get the instruction's basic block.
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
// Get the basic block's function.
|
|
MachineFunction &MF = *MBB.getParent();
|
|
// Get the frame info.
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
DebugLoc dl = MI.getDebugLoc();
|
|
|
|
// Find out which operand is the frame index.
|
|
unsigned FIOperandNo = 0;
|
|
while (!MI.getOperand(FIOperandNo).isFI()) {
|
|
++FIOperandNo;
|
|
assert(FIOperandNo != MI.getNumOperands() &&
|
|
"Instr doesn't have FrameIndex operand!");
|
|
}
|
|
// Take into account whether it's an add or mem instruction
|
|
unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
|
|
if (MI.isInlineAsm())
|
|
OffsetOperandNo = FIOperandNo-1;
|
|
|
|
// Get the frame index.
|
|
int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
|
|
|
|
// Get the frame pointer save index. Users of this index are primarily
|
|
// DYNALLOC instructions.
|
|
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
int FPSI = FI->getFramePointerSaveIndex();
|
|
// Get the instruction opcode.
|
|
unsigned OpC = MI.getOpcode();
|
|
|
|
// Special case for dynamic alloca.
|
|
if (FPSI && FrameIndex == FPSI &&
|
|
(OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
|
|
lowerDynamicAlloc(II, SPAdj, RS);
|
|
return;
|
|
}
|
|
|
|
// Special case for pseudo-ops SPILL_CR and RESTORE_CR.
|
|
if (requiresRegisterScavenging(MF)) {
|
|
if (OpC == PPC::SPILL_CR) {
|
|
lowerCRSpilling(II, FrameIndex, SPAdj, RS);
|
|
return;
|
|
} else if (OpC == PPC::RESTORE_CR) {
|
|
lowerCRRestore(II, FrameIndex, SPAdj, RS);
|
|
return;
|
|
}
|
|
}
|
|
|
|
// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
|
|
|
|
bool is64Bit = Subtarget.isPPC64();
|
|
MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ?
|
|
(is64Bit ? PPC::X31 : PPC::R31) :
|
|
(is64Bit ? PPC::X1 : PPC::R1),
|
|
false);
|
|
|
|
// Figure out if the offset in the instruction is shifted right two bits. This
|
|
// is true for instructions like "STD", which the machine implicitly adds two
|
|
// low zeros to.
|
|
bool isIXAddr = false;
|
|
switch (OpC) {
|
|
case PPC::LWA:
|
|
case PPC::LD:
|
|
case PPC::STD:
|
|
case PPC::STD_32:
|
|
isIXAddr = true;
|
|
break;
|
|
}
|
|
|
|
// Now add the frame object offset to the offset from r1.
|
|
int Offset = MFI->getObjectOffset(FrameIndex);
|
|
if (!isIXAddr)
|
|
Offset += MI.getOperand(OffsetOperandNo).getImm();
|
|
else
|
|
Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
|
|
|
|
// If we're not using a Frame Pointer that has been set to the value of the
|
|
// SP before having the stack size subtracted from it, then add the stack size
|
|
// to Offset to get the correct offset.
|
|
// Naked functions have stack size 0, although getStackSize may not reflect that
|
|
// because we didn't call all the pieces that compute it for naked functions.
|
|
if (!MF.getFunction()->hasFnAttr(Attribute::Naked))
|
|
Offset += MFI->getStackSize();
|
|
|
|
// If we can, encode the offset directly into the instruction. If this is a
|
|
// normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
|
|
// this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
|
|
// clear can be encoded. This is extremely uncommon, because normally you
|
|
// only "std" to a stack slot that is at least 4-byte aligned, but it can
|
|
// happen in invalid code.
|
|
if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
|
|
(isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) {
|
|
if (isIXAddr)
|
|
Offset >>= 2; // The actual encoded value has the low two bits zero.
|
|
MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
|
|
return;
|
|
}
|
|
|
|
// The offset doesn't fit into a single register, scavenge one to build the
|
|
// offset in.
|
|
|
|
unsigned SReg;
|
|
if (requiresRegisterScavenging(MF)) {
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
SReg = findScratchRegister(II, RS, is64Bit ? G8RC : GPRC, SPAdj);
|
|
} else
|
|
SReg = is64Bit ? PPC::X0 : PPC::R0;
|
|
|
|
// Insert a set of rA with the full offset value before the ld, st, or add
|
|
BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg)
|
|
.addImm(Offset >> 16);
|
|
BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
|
|
.addReg(SReg, RegState::Kill)
|
|
.addImm(Offset);
|
|
|
|
// Convert into indexed form of the instruction:
|
|
//
|
|
// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
|
|
// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
|
|
unsigned OperandBase;
|
|
|
|
if (OpC != TargetOpcode::INLINEASM) {
|
|
assert(ImmToIdxMap.count(OpC) &&
|
|
"No indexed form of load or store available!");
|
|
unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
|
|
MI.setDesc(TII.get(NewOpcode));
|
|
OperandBase = 1;
|
|
} else {
|
|
OperandBase = OffsetOperandNo;
|
|
}
|
|
|
|
unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
|
|
MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
|
|
MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
|
|
}
|
|
|
|
unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
|
|
if (!Subtarget.isPPC64())
|
|
return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
|
|
else
|
|
return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
|
|
}
|
|
|
|
unsigned PPCRegisterInfo::getEHExceptionRegister() const {
|
|
return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
|
|
}
|
|
|
|
unsigned PPCRegisterInfo::getEHHandlerRegister() const {
|
|
return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
|
|
}
|