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https://github.com/c64scene-ar/llvm-6502.git
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9a2cfffdb6
* Only apply divide bypass optimization when not optimizing for size. * Fixed bug caused by constant for 0 value of type Int32, used dividend type to generate the constant instead. * For atom x86-64 apply the divide bypass to use 16-bit divides instead of 64-bit divides when operand values are small enough. * Added lit tests for 64-bit divide bypass. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176442 91177308-0d34-0410-b5e6-96231b3b80d8
113 lines
2.4 KiB
LLVM
113 lines
2.4 KiB
LLVM
; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s
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define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind {
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; CHECK: Test_get_quotient:
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; CHECK: orl %ecx, %edx
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; CHECK-NEXT: testl $-256, %edx
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; CHECK-NEXT: je
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; CHECK: idivl
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; CHECK: ret
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; CHECK: divb
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; CHECK: ret
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%result = sdiv i32 %a, %b
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ret i32 %result
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}
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define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind {
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; CHECK: Test_get_remainder:
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; CHECK: orl %ecx, %edx
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; CHECK-NEXT: testl $-256, %edx
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; CHECK-NEXT: je
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; CHECK: idivl
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; CHECK: ret
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; CHECK: divb
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; CHECK: ret
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%result = srem i32 %a, %b
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ret i32 %result
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}
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define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind {
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; CHECK: Test_get_quotient_and_remainder:
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; CHECK: orl %ecx, %edx
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; CHECK-NEXT: testl $-256, %edx
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; CHECK-NEXT: je
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; CHECK: idivl
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; CHECK: divb
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; CHECK: addl
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; CHECK: ret
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; CHECK-NOT: idivl
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; CHECK-NOT: divb
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%resultdiv = sdiv i32 %a, %b
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%resultrem = srem i32 %a, %b
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%result = add i32 %resultdiv, %resultrem
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ret i32 %result
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}
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define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {
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; CHECK: Test_use_div_and_idiv:
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; CHECK: idivl
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; CHECK: divb
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; CHECK: divl
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; CHECK: divb
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; CHECK: addl
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; CHECK: ret
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%resultidiv = sdiv i32 %a, %b
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%resultdiv = udiv i32 %a, %b
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%result = add i32 %resultidiv, %resultdiv
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ret i32 %result
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}
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define i32 @Test_use_div_imm_imm() nounwind {
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; CHECK: Test_use_div_imm_imm:
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; CHECK: movl $64
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%resultdiv = sdiv i32 256, 4
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ret i32 %resultdiv
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}
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define i32 @Test_use_div_reg_imm(i32 %a) nounwind {
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; CHECK: Test_use_div_reg_imm:
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; CHECK-NOT: test
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; CHECK-NOT: idiv
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; CHECK-NOT: divb
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%resultdiv = sdiv i32 %a, 33
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ret i32 %resultdiv
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}
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define i32 @Test_use_rem_reg_imm(i32 %a) nounwind {
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; CHECK: Test_use_rem_reg_imm:
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; CHECK-NOT: test
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; CHECK-NOT: idiv
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; CHECK-NOT: divb
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%resultrem = srem i32 %a, 33
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ret i32 %resultrem
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}
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define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {
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; CHECK: Test_use_divrem_reg_imm:
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; CHECK-NOT: test
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; CHECK-NOT: idiv
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; CHECK-NOT: divb
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%resultdiv = sdiv i32 %a, 33
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%resultrem = srem i32 %a, 33
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%result = add i32 %resultdiv, %resultrem
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ret i32 %result
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}
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define i32 @Test_use_div_imm_reg(i32 %a) nounwind {
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; CHECK: Test_use_div_imm_reg:
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; CHECK: test
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; CHECK: idiv
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; CHECK: divb
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%resultdiv = sdiv i32 4, %a
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ret i32 %resultdiv
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}
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define i32 @Test_use_rem_imm_reg(i32 %a) nounwind {
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; CHECK: Test_use_rem_imm_reg:
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; CHECK: test
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; CHECK: idiv
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; CHECK: divb
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%resultdiv = sdiv i32 4, %a
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ret i32 %resultdiv
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}
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