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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31464 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
1.7 KiB
C++
48 lines
1.7 KiB
C++
//===- PromoteMemToReg.h - Promote Allocas to Scalars -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file exposes an interface to promote alloca instructions to SSA
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// registers, by using the SSA construction algorithm.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TRANSFORMS_UTILS_PROMOTEMEMTOREG_H
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#define TRANSFORMS_UTILS_PROMOTEMEMTOREG_H
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#include <vector>
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namespace llvm {
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class AllocaInst;
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class DominatorTree;
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class DominanceFrontier;
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class TargetData;
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class AliasSetTracker;
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/// isAllocaPromotable - Return true if this alloca is legal for promotion.
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/// This is true if there are only loads and stores to the alloca...
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///
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bool isAllocaPromotable(const AllocaInst *AI, const TargetData &TD);
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/// PromoteMemToReg - Promote the specified list of alloca instructions into
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/// scalar registers, inserting PHI nodes as appropriate. This function makes
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/// use of DominanceFrontier information. This function does not modify the CFG
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/// of the function at all. All allocas must be from the same function.
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///
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/// If AST is specified, the specified tracker is updated to reflect changes
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/// made to the IR.
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///
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void PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,
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DominatorTree &DT, DominanceFrontier &DF,
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const TargetData &TD, AliasSetTracker *AST = 0);
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} // End llvm namespace
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#endif
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