mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-17 18:10:31 +00:00
5d598aaf3d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
130 lines
5.7 KiB
TableGen
130 lines
5.7 KiB
TableGen
//===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Functional units across ARM processors
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//
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def FU_Issue : FuncUnit; // issue
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def FU_Pipe0 : FuncUnit; // pipeline 0
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def FU_Pipe1 : FuncUnit; // pipeline 1
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def FU_LdSt0 : FuncUnit; // pipeline 0 load/store
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def FU_LdSt1 : FuncUnit; // pipeline 1 load/store
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for ARM
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//
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def IIC_iALUx : InstrItinClass;
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def IIC_iALUi : InstrItinClass;
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def IIC_iALUr : InstrItinClass;
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def IIC_iALUsi : InstrItinClass;
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def IIC_iALUsr : InstrItinClass;
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def IIC_iUNAr : InstrItinClass;
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def IIC_iUNAsi : InstrItinClass;
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def IIC_iUNAsr : InstrItinClass;
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def IIC_iCMPi : InstrItinClass;
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def IIC_iCMPr : InstrItinClass;
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def IIC_iCMPsi : InstrItinClass;
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def IIC_iCMPsr : InstrItinClass;
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def IIC_iMOVi : InstrItinClass;
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def IIC_iMOVr : InstrItinClass;
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def IIC_iMOVsi : InstrItinClass;
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def IIC_iMOVsr : InstrItinClass;
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def IIC_iCMOVi : InstrItinClass;
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def IIC_iCMOVr : InstrItinClass;
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def IIC_iCMOVsi : InstrItinClass;
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def IIC_iCMOVsr : InstrItinClass;
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def IIC_iMUL16 : InstrItinClass;
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def IIC_iMAC16 : InstrItinClass;
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def IIC_iMUL32 : InstrItinClass;
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def IIC_iMAC32 : InstrItinClass;
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def IIC_iMUL64 : InstrItinClass;
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def IIC_iMAC64 : InstrItinClass;
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def IIC_iLoadi : InstrItinClass;
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def IIC_iLoadr : InstrItinClass;
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def IIC_iLoadsi : InstrItinClass;
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def IIC_iLoadiu : InstrItinClass;
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def IIC_iLoadru : InstrItinClass;
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def IIC_iLoadsiu : InstrItinClass;
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def IIC_iLoadm : InstrItinClass;
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def IIC_iStorei : InstrItinClass;
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def IIC_iStorer : InstrItinClass;
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def IIC_iStoresi : InstrItinClass;
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def IIC_iStoreiu : InstrItinClass;
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def IIC_iStoreru : InstrItinClass;
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def IIC_iStoresiu : InstrItinClass;
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def IIC_iStorem : InstrItinClass;
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def IIC_fpALU : InstrItinClass;
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def IIC_fpMPY : InstrItinClass;
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def IIC_fpLoad : InstrItinClass;
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def IIC_fpStore : InstrItinClass;
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def IIC_Br : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Processor instruction itineraries.
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def GenericItineraries : ProcessorItineraries<[
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InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Pipe0]>,
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InstrStage<2, [FU_LdSt0]>]>,
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InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Pipe0]>]>,
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InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>
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]>;
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include "ARMScheduleV6.td"
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include "ARMScheduleV7.td"
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