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fact that all ExternalSymbols are actually string literals with static storage. Thus we don't have to do anything special to hold them and we certainly don't have to copy string data around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18007 91177308-0d34-0410-b5e6-96231b3b80d8
776 lines
27 KiB
C++
776 lines
27 KiB
C++
//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the declaration of the MachineInstr class, which is the
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// basic representation for all target dependent machine instructions used by
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// the back end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEINSTR_H
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#define LLVM_CODEGEN_MACHINEINSTR_H
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#include "llvm/ADT/iterator"
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#include <vector>
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#include <cassert>
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namespace llvm {
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class Value;
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class Function;
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class MachineBasicBlock;
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class TargetMachine;
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class GlobalValue;
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template <typename T> struct ilist_traits;
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template <typename T> struct ilist;
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typedef short MachineOpCode;
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//===----------------------------------------------------------------------===//
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// class MachineOperand
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//
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// Purpose:
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// Representation of each machine instruction operand.
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// This class is designed so that you can allocate a vector of operands
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// first and initialize each one later.
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//
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// E.g, for this VM instruction:
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// ptr = alloca type, numElements
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// we generate 2 machine instructions on the SPARC:
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//
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// mul Constant, Numelements -> Reg
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// add %sp, Reg -> Ptr
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//
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// Each instruction has 3 operands, listed above. Of those:
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// - Reg, NumElements, and Ptr are of operand type MO_Register.
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// - Constant is of operand type MO_SignExtendedImmed on the SPARC.
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//
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// For the register operands, the virtual register type is as follows:
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//
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// - Reg will be of virtual register type MO_MInstrVirtualReg. The field
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// MachineInstr* minstr will point to the instruction that computes reg.
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//
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// - %sp will be of virtual register type MO_MachineReg.
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// The field regNum identifies the machine register.
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//
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// - NumElements will be of virtual register type MO_VirtualReg.
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// The field Value* value identifies the value.
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//
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// - Ptr will also be of virtual register type MO_VirtualReg.
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// Again, the field Value* value identifies the value.
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//
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//===----------------------------------------------------------------------===//
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struct MachineOperand {
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private:
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// Bit fields of the flags variable used for different operand properties
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enum {
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DEFFLAG = 0x01, // this is a def of the operand
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USEFLAG = 0x02, // this is a use of the operand
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HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
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LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
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HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
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LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
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PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
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};
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public:
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// UseType - This enum describes how the machine operand is used by
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// the instruction. Note that the MachineInstr/Operator class
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// currently uses bool arguments to represent this information
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// instead of an enum. Eventually this should change over to use
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// this _easier to read_ representation instead.
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//
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enum UseType {
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Use = USEFLAG, /// only read
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Def = DEFFLAG, /// only written
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UseAndDef = Use | Def /// read AND written
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};
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enum MachineOperandType {
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MO_VirtualRegister, // virtual register for *value
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MO_MachineRegister, // pre-assigned machine register `regNum'
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MO_CCRegister,
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MO_SignExtendedImmed,
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MO_UnextendedImmed,
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MO_PCRelativeDisp,
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MO_MachineBasicBlock, // MachineBasicBlock reference
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MO_FrameIndex, // Abstract Stack Frame Index
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MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
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MO_ExternalSymbol, // Name of external global symbol
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MO_GlobalAddress, // Address of a global value
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};
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private:
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union {
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Value* value; // BasicBlockVal for a label operand.
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// ConstantVal for a non-address immediate.
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// Virtual register for an SSA operand,
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// including hidden operands required for
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// the generated machine code.
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// LLVM global for MO_GlobalAddress.
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int immedVal; // Constant value for an explicit constant
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MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
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const char *SymbolName; // For MO_ExternalSymbol type
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} contents;
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char flags; // see bit field definitions above
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MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
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union {
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int regNum; // register number for an explicit register
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// will be set for a value after reg allocation
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int offset; // Offset to address of global or external, only
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// valid for MO_GlobalAddress and MO_ExternalSym
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} extra;
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void zeroContents () {
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memset (&contents, 0, sizeof (contents));
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memset (&extra, 0, sizeof (extra));
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}
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MachineOperand(int ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister)
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: flags(0), opType(OpTy) {
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zeroContents ();
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contents.immedVal = ImmVal;
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extra.regNum = -1;
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}
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MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy)
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: flags(UseTy), opType(OpTy) {
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zeroContents ();
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extra.regNum = Reg;
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}
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MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy,
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bool isPCRelative = false)
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: flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
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assert(OpTy != MachineOperand::MO_GlobalAddress);
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zeroContents();
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contents.value = V;
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extra.regNum = -1;
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}
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MachineOperand(GlobalValue *V, MachineOperandType OpTy, UseType UseTy,
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bool isPCRelative = false, int Offset = 0)
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: flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
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assert(OpTy == MachineOperand::MO_GlobalAddress);
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zeroContents ();
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contents.value = (Value*)V;
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extra.offset = Offset;
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}
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MachineOperand(MachineBasicBlock *mbb)
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: flags(0), opType(MO_MachineBasicBlock) {
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zeroContents ();
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contents.MBB = mbb;
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extra.regNum = -1;
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}
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MachineOperand(const char *SymName, bool isPCRelative, int Offset)
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: flags(isPCRelative?PCRELATIVE:0), opType(MO_ExternalSymbol) {
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zeroContents ();
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contents.SymbolName = SymName;
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extra.offset = Offset;
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}
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public:
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MachineOperand(const MachineOperand &M)
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: flags(M.flags), opType(M.opType) {
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zeroContents ();
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contents = M.contents;
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extra = M.extra;
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}
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~MachineOperand() {}
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const MachineOperand &operator=(const MachineOperand &MO) {
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contents = MO.contents;
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flags = MO.flags;
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opType = MO.opType;
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extra = MO.extra;
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return *this;
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}
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/// getType - Returns the MachineOperandType for this operand.
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///
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MachineOperandType getType() const { return opType; }
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/// getUseType - Returns the MachineOperandUseType of this operand.
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///
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UseType getUseType() const { return UseType(flags & (USEFLAG|DEFFLAG)); }
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/// isPCRelative - This returns the value of the PCRELATIVE flag, which
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/// indicates whether this operand should be emitted as a PC relative value
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/// instead of a global address. This is used for operands of the forms:
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/// MachineBasicBlock, GlobalAddress, ExternalSymbol
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///
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bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
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/// isRegister - Return true if this operand is a register operand. The X86
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/// backend currently can't decide whether to use MO_MR or MO_VR to represent
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/// them, so we accept both.
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///
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/// Note: The sparc backend should not use this method.
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///
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bool isRegister() const {
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return opType == MO_MachineRegister || opType == MO_VirtualRegister;
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}
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/// Accessors that tell you what kind of MachineOperand you're looking at.
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///
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bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
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bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
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bool isImmediate() const {
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return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
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}
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bool isFrameIndex() const { return opType == MO_FrameIndex; }
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bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
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bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
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bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
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/// getVRegValueOrNull - Get the Value* out of a MachineOperand if it
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/// has one. This is deprecated and only used by the SPARC v9 backend.
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///
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Value* getVRegValueOrNull() const {
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return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
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isPCRelativeDisp()) ? contents.value : NULL;
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}
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/// MachineOperand accessors that only work on certain types of
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/// MachineOperand...
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///
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Value* getVRegValue() const {
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assert ((opType == MO_VirtualRegister || opType == MO_CCRegister
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|| isPCRelativeDisp()) && "Wrong MachineOperand accessor");
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return contents.value;
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}
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int getMachineRegNum() const {
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assert(opType == MO_MachineRegister && "Wrong MachineOperand accessor");
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return extra.regNum;
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}
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int getImmedValue() const {
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assert(isImmediate() && "Wrong MachineOperand accessor");
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return contents.immedVal;
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}
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MachineBasicBlock *getMachineBasicBlock() const {
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assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
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return contents.MBB;
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}
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void setMachineBasicBlock(MachineBasicBlock *MBB) {
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assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
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contents.MBB = MBB;
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}
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int getFrameIndex() const {
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assert(isFrameIndex() && "Wrong MachineOperand accessor");
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return contents.immedVal;
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}
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unsigned getConstantPoolIndex() const {
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assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
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return contents.immedVal;
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}
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GlobalValue *getGlobal() const {
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assert(isGlobalAddress() && "Wrong MachineOperand accessor");
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return (GlobalValue*)contents.value;
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}
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int getOffset() const {
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assert((isGlobalAddress() || isExternalSymbol()) &&
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"Wrong MachineOperand accessor");
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return extra.offset;
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}
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const char *getSymbolName() const {
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assert(isExternalSymbol() && "Wrong MachineOperand accessor");
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return contents.SymbolName;
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}
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/// MachineOperand methods for testing that work on any kind of
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/// MachineOperand...
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///
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bool isUse () const { return flags & USEFLAG; }
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MachineOperand& setUse () { flags |= USEFLAG; return *this; }
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bool isDef () const { return flags & DEFFLAG; }
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MachineOperand& setDef () { flags |= DEFFLAG; return *this; }
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bool isHiBits32 () const { return flags & HIFLAG32; }
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bool isLoBits32 () const { return flags & LOFLAG32; }
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bool isHiBits64 () const { return flags & HIFLAG64; }
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bool isLoBits64 () const { return flags & LOFLAG64; }
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/// hasAllocatedReg - Returns true iff a machine register has been
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/// allocated to this operand.
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///
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bool hasAllocatedReg() const {
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return (extra.regNum >= 0 &&
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(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister));
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}
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/// getReg - Returns the register number. It is a runtime error to call this
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/// if a register is not allocated.
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///
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unsigned getReg() const {
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assert(hasAllocatedReg());
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return extra.regNum;
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}
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/// MachineOperand mutators...
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///
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void setReg(unsigned Reg) {
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// This method's comment used to say: 'TODO: get rid of this duplicate
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// code.' It's not clear where the duplication is.
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assert(hasAllocatedReg() && "This operand cannot have a register number!");
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extra.regNum = Reg;
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}
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void setValueReg(Value *val) {
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assert(getVRegValueOrNull() != 0 && "Original operand must of type Value*");
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contents.value = val;
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}
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void setImmedValue(int immVal) {
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assert(isImmediate() && "Wrong MachineOperand mutator");
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contents.immedVal = immVal;
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}
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void setOffset(int Offset) {
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assert((isGlobalAddress() || isExternalSymbol()) &&
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"Wrong MachineOperand accessor");
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extra.offset = Offset;
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}
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friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
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/// markHi32, markLo32, etc. - These methods are deprecated and only used by
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/// the SPARC v9 back-end.
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///
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void markHi32() { flags |= HIFLAG32; }
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void markLo32() { flags |= LOFLAG32; }
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void markHi64() { flags |= HIFLAG64; }
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void markLo64() { flags |= LOFLAG64; }
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private:
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/// setRegForValue - Replaces the Value with its corresponding physical
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/// register after register allocation is complete. This is deprecated
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/// and only used by the SPARC v9 back-end.
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///
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void setRegForValue(int reg) {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister);
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extra.regNum = reg;
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}
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friend class MachineInstr;
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};
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//===----------------------------------------------------------------------===//
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// class MachineInstr
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//
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// Purpose:
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// Representation of each machine instruction.
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//
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// MachineOpCode must be an enum, defined separately for each target.
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// E.g., It is defined in SparcInstructionSelection.h for the SPARC.
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//
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// There are 2 kinds of operands:
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//
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// (1) Explicit operands of the machine instruction in vector operands[]
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//
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// (2) "Implicit operands" are values implicitly used or defined by the
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// machine instruction, such as arguments to a CALL, return value of
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// a CALL (if any), and return value of a RETURN.
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//===----------------------------------------------------------------------===//
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class MachineInstr {
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short Opcode; // the opcode
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unsigned char numImplicitRefs; // number of implicit operands
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std::vector<MachineOperand> operands; // the operands
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MachineInstr* prev, *next; // links for our intrusive list
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MachineBasicBlock* parent; // pointer to the owning basic block
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// OperandComplete - Return true if it's illegal to add a new operand
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bool OperandsComplete() const;
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//Constructor used by clone() method
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MachineInstr(const MachineInstr&);
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void operator=(const MachineInstr&); // DO NOT IMPLEMENT
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// Intrusive list support
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//
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friend struct ilist_traits<MachineInstr>;
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public:
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MachineInstr(short Opcode, unsigned numOperands);
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/// MachineInstr ctor - This constructor only does a _reserve_ of the
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/// operands, not a resize for them. It is expected that if you use this that
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/// you call add* methods below to fill up the operands, instead of the Set
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/// methods. Eventually, the "resizing" ctors will be phased out.
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///
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MachineInstr(short Opcode, unsigned numOperands, bool XX, bool YY);
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/// MachineInstr ctor - Work exactly the same as the ctor above, except that
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/// the MachineInstr is created and added to the end of the specified basic
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/// block.
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///
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MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps);
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~MachineInstr();
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const MachineBasicBlock* getParent() const { return parent; }
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MachineBasicBlock* getParent() { return parent; }
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/// getOpcode - Returns the opcode of this MachineInstr.
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///
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const int getOpcode() const { return Opcode; }
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/// Access to explicit operands of the instruction.
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///
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unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
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const MachineOperand& getOperand(unsigned i) const {
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assert(i < getNumOperands() && "getOperand() out of range!");
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return operands[i];
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}
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MachineOperand& getOperand(unsigned i) {
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assert(i < getNumOperands() && "getOperand() out of range!");
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return operands[i];
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}
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//
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// Access to explicit or implicit operands of the instruction
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// This returns the i'th entry in the operand vector.
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// That represents the i'th explicit operand or the (i-N)'th implicit operand,
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// depending on whether i < N or i >= N.
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//
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const MachineOperand& getExplOrImplOperand(unsigned i) const {
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assert(i < operands.size() && "getExplOrImplOperand() out of range!");
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return (i < getNumOperands()? getOperand(i)
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: getImplicitOp(i - getNumOperands()));
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}
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//
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// Access to implicit operands of the instruction
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//
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unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
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MachineOperand& getImplicitOp(unsigned i) {
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assert(i < numImplicitRefs && "implicit ref# out of range!");
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return operands[i + operands.size() - numImplicitRefs];
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}
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const MachineOperand& getImplicitOp(unsigned i) const {
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assert(i < numImplicitRefs && "implicit ref# out of range!");
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return operands[i + operands.size() - numImplicitRefs];
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}
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Value* getImplicitRef(unsigned i) {
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return getImplicitOp(i).getVRegValue();
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}
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const Value* getImplicitRef(unsigned i) const {
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return getImplicitOp(i).getVRegValue();
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}
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void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) {
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++numImplicitRefs;
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addRegOperand(V, isDef, isDefAndUse);
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}
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void setImplicitRef(unsigned i, Value* V) {
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assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
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SetMachineOperandVal(i + getNumOperands(),
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MachineOperand::MO_VirtualRegister, V);
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}
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/// clone - Create a copy of 'this' instruction that is identical in
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/// all ways except the the instruction has no parent, prev, or next.
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MachineInstr* clone() const;
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//
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// Debugging support
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//
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void print(std::ostream &OS, const TargetMachine *TM) const;
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void dump() const;
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friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
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//
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// Define iterators to access the Value operands of the Machine Instruction.
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// Note that these iterators only enumerate the explicit operands.
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// begin() and end() are defined to produce these iterators...
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//
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template<class _MI, class _V> class ValOpIterator;
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typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
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typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
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//===--------------------------------------------------------------------===//
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// Accessors to add operands when building up machine instructions
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//
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/// addRegOperand - Add a MO_VirtualRegister operand to the end of the
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/// operands list...
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///
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void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(
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MachineOperand(V, MachineOperand::MO_VirtualRegister,
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!isDef ? MachineOperand::Use :
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(isDefAndUse ? MachineOperand::UseAndDef :
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MachineOperand::Def)));
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}
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void addRegOperand(Value *V,
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MachineOperand::UseType UTy = MachineOperand::Use,
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bool isPCRelative = false) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
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UTy, isPCRelative));
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}
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void addCCRegOperand(Value *V,
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MachineOperand::UseType UTy = MachineOperand::Use) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
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false));
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}
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/// addRegOperand - Add a symbolic virtual register reference...
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///
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void addRegOperand(int reg, bool isDef) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(
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MachineOperand(reg, MachineOperand::MO_VirtualRegister,
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isDef ? MachineOperand::Def : MachineOperand::Use));
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}
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/// addRegOperand - Add a symbolic virtual register reference...
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///
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void addRegOperand(int reg,
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MachineOperand::UseType UTy = MachineOperand::Use) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(
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MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy));
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}
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/// addPCDispOperand - Add a PC relative displacement operand to the MI
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///
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void addPCDispOperand(Value *V) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(
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MachineOperand(V, MachineOperand::MO_PCRelativeDisp,MachineOperand::Use));
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}
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/// addMachineRegOperand - Add a virtual register operand to this MachineInstr
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///
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void addMachineRegOperand(int reg, bool isDef) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(
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MachineOperand(reg, MachineOperand::MO_MachineRegister,
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isDef ? MachineOperand::Def : MachineOperand::Use));
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}
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/// addMachineRegOperand - Add a virtual register operand to this MachineInstr
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///
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void addMachineRegOperand(int reg,
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MachineOperand::UseType UTy = MachineOperand::Use) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(
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MachineOperand(reg, MachineOperand::MO_MachineRegister, UTy));
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}
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/// addZeroExtImmOperand - Add a zero extended constant argument to the
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/// machine instruction.
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///
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void addZeroExtImmOperand(int intValue) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(
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MachineOperand(intValue, MachineOperand::MO_UnextendedImmed));
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}
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/// addSignExtImmOperand - Add a zero extended constant argument to the
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/// machine instruction.
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///
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void addSignExtImmOperand(int intValue) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(
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MachineOperand(intValue, MachineOperand::MO_SignExtendedImmed));
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}
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void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(MachineOperand(MBB));
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}
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/// addFrameIndexOperand - Add an abstract frame index to the instruction
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///
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void addFrameIndexOperand(unsigned Idx) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
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}
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/// addConstantPoolndexOperand - Add a constant pool object index to the
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/// instruction.
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///
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void addConstantPoolIndexOperand(unsigned I) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
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}
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void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative, int Offset) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(
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MachineOperand(GV, MachineOperand::MO_GlobalAddress,
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MachineOperand::Use, isPCRelative, Offset));
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}
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/// addExternalSymbolOperand - Add an external symbol operand to this instr
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///
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void addExternalSymbolOperand(const char *SymName, bool isPCRelative) {
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operands.push_back(MachineOperand(SymName, isPCRelative, 0));
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}
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//===--------------------------------------------------------------------===//
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// Accessors used to modify instructions in place.
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//
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// FIXME: Move this stuff to MachineOperand itself!
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/// replace - Support to rewrite a machine instruction in place: for now,
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/// simply replace() and then set new operands with Set.*Operand methods
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/// below.
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///
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void replace(short Opcode, unsigned numOperands);
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/// setOpcode - Replace the opcode of the current instruction with a new one.
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///
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void setOpcode(unsigned Op) { Opcode = Op; }
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/// RemoveOperand - Erase an operand from an instruction, leaving it with one
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/// fewer operand than it started with.
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///
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void RemoveOperand(unsigned i) {
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operands.erase(operands.begin()+i);
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}
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// Access to set the operands when building the machine instruction
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//
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void SetMachineOperandVal(unsigned i,
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MachineOperand::MachineOperandType operandType,
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Value* V);
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void SetMachineOperandConst(unsigned i,
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MachineOperand::MachineOperandType operandType,
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int intValue);
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void SetMachineOperandReg(unsigned i, int regNum);
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unsigned substituteValue(const Value* oldVal, Value* newVal,
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bool defsOnly, bool notDefsAndUses,
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bool& someArgsWereIgnored);
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// SetRegForOperand -
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// SetRegForImplicitRef -
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// Mark an explicit or implicit operand with its allocated physical register.
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//
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void SetRegForOperand(unsigned i, int regNum);
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void SetRegForImplicitRef(unsigned i, int regNum);
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|
|
//
|
|
// Iterator to enumerate machine operands.
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//
|
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template<class MITy, class VTy>
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class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
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unsigned i;
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MITy MI;
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|
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void skipToNextVal() {
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while (i < MI->getNumOperands() &&
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!( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
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MI->getOperand(i).getType() == MachineOperand::MO_CCRegister)
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&& MI->getOperand(i).getVRegValue() != 0))
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++i;
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}
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|
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inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
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skipToNextVal();
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}
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public:
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|
typedef ValOpIterator<MITy, VTy> _Self;
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|
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inline VTy operator*() const {
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return MI->getOperand(i).getVRegValue();
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}
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const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
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MachineOperand &getMachineOperand() { return MI->getOperand(i);}
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|
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inline VTy operator->() const { return operator*(); }
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|
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inline bool isUse() const { return MI->getOperand(i).isUse(); }
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inline bool isDef() const { return MI->getOperand(i).isDef(); }
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inline _Self& operator++() { i++; skipToNextVal(); return *this; }
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inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
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|
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inline bool operator==(const _Self &y) const {
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return i == y.i;
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}
|
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inline bool operator!=(const _Self &y) const {
|
|
return !operator==(y);
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}
|
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|
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static _Self begin(MITy MI) {
|
|
return _Self(MI, 0);
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|
}
|
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static _Self end(MITy MI) {
|
|
return _Self(MI, MI->getNumOperands());
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}
|
|
};
|
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|
|
// define begin() and end()
|
|
val_op_iterator begin() { return val_op_iterator::begin(this); }
|
|
val_op_iterator end() { return val_op_iterator::end(this); }
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|
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const_val_op_iterator begin() const {
|
|
return const_val_op_iterator::begin(this);
|
|
}
|
|
const_val_op_iterator end() const {
|
|
return const_val_op_iterator::end(this);
|
|
}
|
|
};
|
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|
|
//===----------------------------------------------------------------------===//
|
|
// Debugging Support
|
|
|
|
std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
|
|
std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
|
|
void PrintMachineInstructions(const Function *F);
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|
|
|
} // End llvm namespace
|
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|
#endif
|