llvm-6502/lib/Target/X86
Chris Lattner ffff6175ef add a note that Nate mentioned last week
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23898 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-23 21:44:59 +00:00
..
.cvsignore
Makefile
README.txt add a note that Nate mentioned last week 2005-10-23 21:44:59 +00:00
X86.h Remove the X86 and PowerPC Simple instruction selectors; their time has 2005-08-18 23:53:15 +00:00
X86.td
X86AsmPrinter.cpp Eliminate all remaining tabs and trailing spaces. 2005-07-27 06:12:32 +00:00
X86AsmPrinter.h
X86ATTAsmPrinter.cpp Eliminate all remaining tabs and trailing spaces. 2005-07-27 06:12:32 +00:00
X86ATTAsmPrinter.h
X86CodeEmitter.cpp
X86ELFWriter.cpp
X86FloatingPoint.cpp Adjust to new livevars interface 2005-08-23 23:41:14 +00:00
X86InstrBuilder.h
X86InstrInfo.cpp Properly split f32 and f64 into separate register classes for scalar sse fp 2005-10-14 22:06:00 +00:00
X86InstrInfo.h Eliminate tabs and trailing spaces. 2005-07-27 05:53:44 +00:00
X86InstrInfo.td Properly split f32 and f64 into separate register classes for scalar sse fp 2005-10-14 22:06:00 +00:00
X86IntelAsmPrinter.cpp
X86IntelAsmPrinter.h
X86ISelPattern.cpp Invert the TargetLowering flag that controls divide by consant expansion. 2005-10-21 00:02:42 +00:00
X86JITInfo.cpp
X86JITInfo.h turn off GOT on archs that didn't use it (not that it appeard to harm them much with it on) 2005-07-29 23:32:02 +00:00
X86PeepholeOpt.cpp Eliminate all remaining tabs and trailing spaces. 2005-07-27 06:12:32 +00:00
X86RegisterInfo.cpp Properly split f32 and f64 into separate register classes for scalar sse fp 2005-10-14 22:06:00 +00:00
X86RegisterInfo.h Pass extra regclasses into spilling code 2005-09-30 01:29:42 +00:00
X86RegisterInfo.td Properly split f32 and f64 into separate register classes for scalar sse fp 2005-10-14 22:06:00 +00:00
X86Relocations.h
X86Subtarget.cpp 1. Use SubtargetFeatures in llc/lli. 2005-09-01 21:38:21 +00:00
X86Subtarget.h 1. Use SubtargetFeatures in llc/lli. 2005-09-01 21:38:21 +00:00
X86TargetMachine.cpp 1. Use SubtargetFeatures in llc/lli. 2005-09-01 21:38:21 +00:00
X86TargetMachine.h 1. Use SubtargetFeatures in llc/lli. 2005-09-01 21:38:21 +00:00

//===---------------------------------------------------------------------===//
// Random ideas for the X86 backend.
//===---------------------------------------------------------------------===//

Add a MUL2U and MUL2S nodes to represent a multiply that returns both the
Hi and Lo parts (combination of MUL and MULH[SU] into one node).  Add this to
X86, & make the dag combiner produce it when needed.  This will eliminate one
imul from the code generated for:

long long test(long long X, long long Y) { return X*Y; }

by using the EAX result from the mul.  We should add a similar node for
DIVREM.

//===---------------------------------------------------------------------===//

This should be one DIV/IDIV instruction, not a libcall:

unsigned test(unsigned long long X, unsigned Y) {
        return X/Y;
}

This can be done trivially with a custom legalizer.  What about overflow 
though?  http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224

//===---------------------------------------------------------------------===//

Need to add support for rotate instructions.

//===---------------------------------------------------------------------===//

Some targets (e.g. athlons) prefer freep to fstp ST(0):
http://gcc.gnu.org/ml/gcc-patches/2004-04/msg00659.html

//===---------------------------------------------------------------------===//

This should use faddi on chips where it is profitable:
double foo(double P, int *I) { return P+*I; }

//===---------------------------------------------------------------------===//

The FP stackifier needs to be global.  Also, it should handle simple permutates
to reduce number of shuffle instructions, e.g. turning:

fld P	->		fld Q
fld Q			fld P
fxch

or:

fxch	->		fucomi
fucomi			jl X
jg X

//===---------------------------------------------------------------------===//

Improvements to the multiply -> shift/add algorithm:
http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html

//===---------------------------------------------------------------------===//

Improve code like this (occurs fairly frequently, e.g. in LLVM):
long long foo(int x) { return 1LL << x; }

http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html

Another useful one would be  ~0ULL >> X and ~0ULL << X.

//===---------------------------------------------------------------------===//

Should support emission of the bswap instruction, probably by adding a new
DAG node for byte swapping.  Also useful on PPC which has byte-swapping loads.