llvm-6502/test/CodeGen
Bob Wilson bb7ecb2bf5 Thumb2 RSBS instructions were being printed without the 'S' suffix.
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:44:06 +00:00
..
Alpha
ARM LR is in GPR, not tGPR even in Thumb1 mode. 2010-05-24 18:00:18 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic
MBlaze
Mips
MSP430
PIC16
PowerPC Only use clairvoyance when defining a register, and then only if it has one use. 2010-05-17 04:50:57 +00:00
SPARC
SystemZ
Thumb
Thumb2 Thumb2 RSBS instructions were being printed without the 'S' suffix. 2010-05-24 18:44:06 +00:00
X86 This test is darwin only. Make it so(tm). 2010-05-22 00:55:55 +00:00
XCore