mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-05 13:09:10 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
212 lines
5.4 KiB
LLVM
212 lines
5.4 KiB
LLVM
; Test 32-bit unsigned division and remainder.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i32 @foo()
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; Test register division. The result is in the second of the two registers.
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define void @f1(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: %r3
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; CHECK: {{llill|lhi}} %r2, 0
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; CHECK-NOT: %r3
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; CHECK: dlr %r2, %r4
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; CHECK: st %r3, 0(%r5)
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; CHECK: br %r14
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%div = udiv i32 %a, %b
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store i32 %div, i32 *%dest
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ret void
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}
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; Test register remainder. The result is in the first of the two registers.
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define void @f2(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: %r3
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; CHECK: {{llill|lhi}} %r2, 0
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; CHECK-NOT: %r3
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; CHECK: dlr %r2, %r4
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; CHECK: st %r2, 0(%r5)
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; CHECK: br %r14
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%rem = urem i32 %a, %b
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store i32 %rem, i32 *%dest
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ret void
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}
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; Test that division and remainder use a single instruction.
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define i32 @f3(i32 %dummy1, i32 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: %r3
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; CHECK: {{llill|lhi}} %r2, 0
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; CHECK-NOT: %r3
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; CHECK: dlr %r2, %r4
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; CHECK-NOT: dlr
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; CHECK: or %r2, %r3
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; CHECK: br %r14
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%div = udiv i32 %a, %b
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%rem = urem i32 %a, %b
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%or = or i32 %rem, %div
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ret i32 %or
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}
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; Test memory division with no displacement.
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define void @f4(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: %r3
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; CHECK: {{llill|lhi}} %r2, 0
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; CHECK-NOT: %r3
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; CHECK: dl %r2, 0(%r4)
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; CHECK: st %r3, 0(%r5)
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; CHECK: br %r14
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%b = load i32 , i32 *%src
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%div = udiv i32 %a, %b
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store i32 %div, i32 *%dest
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ret void
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}
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; Test memory remainder with no displacement.
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define void @f5(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: %r3
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; CHECK: {{llill|lhi}} %r2, 0
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; CHECK-NOT: %r3
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; CHECK: dl %r2, 0(%r4)
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; CHECK: st %r2, 0(%r5)
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; CHECK: br %r14
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%b = load i32 , i32 *%src
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%rem = urem i32 %a, %b
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store i32 %rem, i32 *%dest
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ret void
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}
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; Test both memory division and memory remainder.
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define i32 @f6(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK-LABEL: f6:
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; CHECK-NOT: %r3
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; CHECK: {{llill|lhi}} %r2, 0
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; CHECK-NOT: %r3
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; CHECK: dl %r2, 0(%r4)
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; CHECK-NOT: {{dl|dlr}}
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; CHECK: or %r2, %r3
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; CHECK: br %r14
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%b = load i32 , i32 *%src
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%div = udiv i32 %a, %b
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%rem = urem i32 %a, %b
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%or = or i32 %rem, %div
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ret i32 %or
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}
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; Check the high end of the DL range.
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define i32 @f7(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK-LABEL: f7:
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; CHECK: dl %r2, 524284(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131071
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%b = load i32 , i32 *%ptr
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%rem = urem i32 %a, %b
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ret i32 %rem
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK-LABEL: f8:
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; CHECK: agfi %r4, 524288
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; CHECK: dl %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131072
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%b = load i32 , i32 *%ptr
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%rem = urem i32 %a, %b
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ret i32 %rem
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}
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; Check the high end of the negative aligned DL range.
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define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK-LABEL: f9:
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; CHECK: dl %r2, -4(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -1
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%b = load i32 , i32 *%ptr
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%rem = urem i32 %a, %b
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ret i32 %rem
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}
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; Check the low end of the DL range.
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define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK-LABEL: f10:
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; CHECK: dl %r2, -524288(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131072
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%b = load i32 , i32 *%ptr
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%rem = urem i32 %a, %b
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ret i32 %rem
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK-LABEL: f11:
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; CHECK: agfi %r4, -524292
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; CHECK: dl %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131073
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%b = load i32 , i32 *%ptr
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%rem = urem i32 %a, %b
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ret i32 %rem
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}
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; Check that DL allows an index.
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define i32 @f12(i32 %dummy, i32 %a, i64 %src, i64 %index) {
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; CHECK-LABEL: f12:
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; CHECK: dl %r2, 524287(%r5,%r4)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i32 *
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%b = load i32 , i32 *%ptr
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%rem = urem i32 %a, %b
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ret i32 %rem
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}
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; Check that divisions of spilled values can use DL rather than DLR.
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define i32 @f13(i32 *%ptr0) {
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; CHECK-LABEL: f13:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: dl {{%r[0-9]+}}, 16{{[04]}}(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i32, i32 *%ptr0, i64 2
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%ptr2 = getelementptr i32, i32 *%ptr0, i64 4
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%ptr3 = getelementptr i32, i32 *%ptr0, i64 6
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%ptr4 = getelementptr i32, i32 *%ptr0, i64 8
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%ptr5 = getelementptr i32, i32 *%ptr0, i64 10
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%ptr6 = getelementptr i32, i32 *%ptr0, i64 12
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%ptr7 = getelementptr i32, i32 *%ptr0, i64 14
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%ptr8 = getelementptr i32, i32 *%ptr0, i64 16
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%ptr9 = getelementptr i32, i32 *%ptr0, i64 18
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%val0 = load i32 , i32 *%ptr0
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%val1 = load i32 , i32 *%ptr1
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%val2 = load i32 , i32 *%ptr2
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%val3 = load i32 , i32 *%ptr3
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%val4 = load i32 , i32 *%ptr4
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%val5 = load i32 , i32 *%ptr5
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%val6 = load i32 , i32 *%ptr6
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%val7 = load i32 , i32 *%ptr7
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%val8 = load i32 , i32 *%ptr8
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%val9 = load i32 , i32 *%ptr9
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%ret = call i32 @foo()
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%div0 = udiv i32 %ret, %val0
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%div1 = udiv i32 %div0, %val1
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%div2 = udiv i32 %div1, %val2
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%div3 = udiv i32 %div2, %val3
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%div4 = udiv i32 %div3, %val4
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%div5 = udiv i32 %div4, %val5
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%div6 = udiv i32 %div5, %val6
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%div7 = udiv i32 %div6, %val7
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%div8 = udiv i32 %div7, %val8
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%div9 = udiv i32 %div8, %val9
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ret i32 %div9
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}
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