Matt Arsenault bc247e4afd R600/SI - Add new CI arithmetic instructions. ... Does not yet include larger part required to match v_mad_i64_i32 / v_mad_u64_u32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202077 91177308-0d34-0410-b5e6-96231b3b80d8		2014-02-24 21:01:28 +00:00
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AArch64	[AArch64] Add register constraints to avoid generating STLXR and STXR with unpredictable behavior.	2014-02-21 07:45:48 +00:00
ARM	Use 16 byte stack alignment for NaCl on ARM	2014-02-16 18:59:48 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Make it impossible to have UnknownABI in CodeGen and Integrated Assembler.	2014-02-20 14:58:19 +00:00
MSP430
NVPTX
PowerPC	Add back r201608, r201622, r201624 and r201625	2014-02-19 17:23:20 +00:00
R600	R600/SI - Add new CI arithmetic instructions.	2014-02-24 21:01:28 +00:00
SPARC	SPARC: Implement TRAP lowering. Matches what GCC emits.	2014-02-23 21:43:52 +00:00
SystemZ
Thumb
Thumb2
X86	AVX-512: Fixed encoding of VPTESTMQ	2014-02-23 14:28:35 +00:00
XCore	XCore target: Handle common linkage	2014-02-18 11:21:59 +00:00