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fb0dfbbff7
On x86: (shl V, 1) -> add V,V Hardware support for vector-shift is sparse and in many cases we scalarize the result. Additionally, on sandybridge padd is faster than shl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143311 91177308-0d34-0410-b5e6-96231b3b80d8
21 lines
450 B
LLVM
21 lines
450 B
LLVM
; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
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;CHECK: addXX_test
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;CHECK: padd
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;CHECK: ret
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define <16 x i8> @addXX_test(<16 x i8> %a) {
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%b = add <16 x i8> %a, %a
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ret <16 x i8> %b
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}
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;CHECK: instcombine_test
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;CHECK: padd
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;CHECK: ret
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define <16 x i8> @instcombine_test(<16 x i8> %a) {
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%b = shl <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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ret <16 x i8> %b
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}
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