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https://github.com/c64scene-ar/llvm-6502.git
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623a7e146b
instruction lower optimization" in the pre-RA scheduler. The optimization, rather the hack, was done before MI use-list was available. Now we should be able to implement it in a better way, perhaps in the two-address pass until a MI scheduler is available. Now that the scheduler has to backtrack to handle call sequences. Adding artificial scheduling constraints is just not safe. Furthermore, the hack is not taking all the other scheduling decisions into consideration so it's just as likely to pessimize code. So I view disabling this optimization goodness regardless of PR11314. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144267 91177308-0d34-0410-b5e6-96231b3b80d8
97 lines
3.9 KiB
LLVM
97 lines
3.9 KiB
LLVM
; RUN: llc < %s -march=x86-64 -enable-lsr-nested | FileCheck %s
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;
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; Nested LSR is required to optimize this case.
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; We do not expect to see this form of IR without -enable-iv-rewrite.
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; xfailed for now because the scheduler two-address hack has been disabled.
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; Now it's generating a leal -1 rather than a decq.
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; XFAIL: *
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define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind {
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; CHECK: borf:
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; CHECK-NOT: inc
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; CHECK-NOT: leal 1(
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; CHECK-NOT: leal -1(
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; CHECK: decq
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; CHECK-NEXT: cmpq $-478
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; CHECK: ret
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bb4.thread:
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br label %bb2.outer
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bb2.outer: ; preds = %bb4, %bb4.thread
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%indvar19 = phi i64 [ 0, %bb4.thread ], [ %indvar.next29, %bb4 ] ; <i64> [#uses=3]
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%indvar31 = trunc i64 %indvar19 to i16 ; <i16> [#uses=1]
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%i.0.reg2mem.0.ph = sub i16 639, %indvar31 ; <i16> [#uses=1]
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%0 = zext i16 %i.0.reg2mem.0.ph to i32 ; <i32> [#uses=1]
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%1 = mul i32 %0, 480 ; <i32> [#uses=1]
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%tmp21 = mul i64 %indvar19, -478 ; <i64> [#uses=1]
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br label %bb2
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bb2: ; preds = %bb2, %bb2.outer
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%indvar = phi i64 [ 0, %bb2.outer ], [ %indvar.next, %bb2 ] ; <i64> [#uses=3]
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%indvar16 = trunc i64 %indvar to i16 ; <i16> [#uses=1]
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%ctg2 = getelementptr i8* %out, i64 %tmp21 ; <i8*> [#uses=1]
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%tmp22 = ptrtoint i8* %ctg2 to i64 ; <i64> [#uses=1]
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%tmp24 = sub i64 %tmp22, %indvar ; <i64> [#uses=1]
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%out_addr.0.reg2mem.0 = inttoptr i64 %tmp24 to i8* ; <i8*> [#uses=1]
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%j.0.reg2mem.0 = sub i16 479, %indvar16 ; <i16> [#uses=1]
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%2 = zext i16 %j.0.reg2mem.0 to i32 ; <i32> [#uses=1]
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%3 = add i32 %1, %2 ; <i32> [#uses=9]
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%4 = add i32 %3, -481 ; <i32> [#uses=1]
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%5 = zext i32 %4 to i64 ; <i64> [#uses=1]
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%6 = getelementptr i8* %in, i64 %5 ; <i8*> [#uses=1]
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%7 = load i8* %6, align 1 ; <i8> [#uses=1]
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%8 = add i32 %3, -480 ; <i32> [#uses=1]
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%9 = zext i32 %8 to i64 ; <i64> [#uses=1]
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%10 = getelementptr i8* %in, i64 %9 ; <i8*> [#uses=1]
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%11 = load i8* %10, align 1 ; <i8> [#uses=1]
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%12 = add i32 %3, -479 ; <i32> [#uses=1]
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%13 = zext i32 %12 to i64 ; <i64> [#uses=1]
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%14 = getelementptr i8* %in, i64 %13 ; <i8*> [#uses=1]
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%15 = load i8* %14, align 1 ; <i8> [#uses=1]
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%16 = add i32 %3, -1 ; <i32> [#uses=1]
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%17 = zext i32 %16 to i64 ; <i64> [#uses=1]
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%18 = getelementptr i8* %in, i64 %17 ; <i8*> [#uses=1]
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%19 = load i8* %18, align 1 ; <i8> [#uses=1]
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%20 = zext i32 %3 to i64 ; <i64> [#uses=1]
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%21 = getelementptr i8* %in, i64 %20 ; <i8*> [#uses=1]
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%22 = load i8* %21, align 1 ; <i8> [#uses=1]
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%23 = add i32 %3, 1 ; <i32> [#uses=1]
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%24 = zext i32 %23 to i64 ; <i64> [#uses=1]
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%25 = getelementptr i8* %in, i64 %24 ; <i8*> [#uses=1]
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%26 = load i8* %25, align 1 ; <i8> [#uses=1]
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%27 = add i32 %3, 481 ; <i32> [#uses=1]
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%28 = zext i32 %27 to i64 ; <i64> [#uses=1]
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%29 = getelementptr i8* %in, i64 %28 ; <i8*> [#uses=1]
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%30 = load i8* %29, align 1 ; <i8> [#uses=1]
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%31 = add i32 %3, 480 ; <i32> [#uses=1]
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%32 = zext i32 %31 to i64 ; <i64> [#uses=1]
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%33 = getelementptr i8* %in, i64 %32 ; <i8*> [#uses=1]
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%34 = load i8* %33, align 1 ; <i8> [#uses=1]
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%35 = add i32 %3, 479 ; <i32> [#uses=1]
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%36 = zext i32 %35 to i64 ; <i64> [#uses=1]
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%37 = getelementptr i8* %in, i64 %36 ; <i8*> [#uses=1]
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%38 = load i8* %37, align 1 ; <i8> [#uses=1]
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%39 = add i8 %11, %7 ; <i8> [#uses=1]
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%40 = add i8 %39, %15 ; <i8> [#uses=1]
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%41 = add i8 %40, %19 ; <i8> [#uses=1]
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%42 = add i8 %41, %22 ; <i8> [#uses=1]
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%43 = add i8 %42, %26 ; <i8> [#uses=1]
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%44 = add i8 %43, %30 ; <i8> [#uses=1]
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%45 = add i8 %44, %34 ; <i8> [#uses=1]
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%46 = add i8 %45, %38 ; <i8> [#uses=1]
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store i8 %46, i8* %out_addr.0.reg2mem.0, align 1
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%indvar.next = add i64 %indvar, 1 ; <i64> [#uses=2]
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%exitcond = icmp eq i64 %indvar.next, 478 ; <i1> [#uses=1]
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br i1 %exitcond, label %bb4, label %bb2
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bb4: ; preds = %bb2
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%indvar.next29 = add i64 %indvar19, 1 ; <i64> [#uses=2]
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%exitcond30 = icmp eq i64 %indvar.next29, 638 ; <i1> [#uses=1]
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br i1 %exitcond30, label %return, label %bb2.outer
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return: ; preds = %bb4
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ret void
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}
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