mirror of
https://github.com/c64scene-ar/llvm-6502.git
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14a926f13b
The code to distinguish between unaligned and aligned addresses was already there, so this is mostly just a switch-on-and-test process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182920 91177308-0d34-0410-b5e6-96231b3b80d8
2293 lines
91 KiB
C++
2293 lines
91 KiB
C++
//===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SystemZTargetLowering class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "systemz-lower"
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#include "SystemZISelLowering.h"
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#include "SystemZCallingConv.h"
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#include "SystemZConstantPoolValue.h"
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#include "SystemZMachineFunctionInfo.h"
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#include "SystemZTargetMachine.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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using namespace llvm;
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// Classify VT as either 32 or 64 bit.
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static bool is32Bit(EVT VT) {
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switch (VT.getSimpleVT().SimpleTy) {
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case MVT::i32:
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return true;
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case MVT::i64:
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return false;
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default:
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llvm_unreachable("Unsupported type");
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}
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}
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// Return a version of MachineOperand that can be safely used before the
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// final use.
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static MachineOperand earlyUseOperand(MachineOperand Op) {
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if (Op.isReg())
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Op.setIsKill(false);
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return Op;
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}
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SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
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: TargetLowering(tm, new TargetLoweringObjectFileELF()),
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Subtarget(*tm.getSubtargetImpl()), TM(tm) {
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MVT PtrVT = getPointerTy();
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// Set up the register classes.
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addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
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addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
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addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
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addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
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addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
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// Compute derived properties from the register classes
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computeRegisterProperties();
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// Set up special registers.
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setExceptionPointerRegister(SystemZ::R6D);
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setExceptionSelectorRegister(SystemZ::R7D);
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setStackPointerRegisterToSaveRestore(SystemZ::R15D);
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// TODO: It may be better to default to latency-oriented scheduling, however
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// LLVM's current latency-oriented scheduler can't handle physreg definitions
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// such as SystemZ has with CC, so set this to the register-pressure
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// scheduler, because it can.
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setSchedulingPreference(Sched::RegPressure);
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setBooleanContents(ZeroOrOneBooleanContent);
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setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
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// Instructions are strings of 2-byte aligned 2-byte values.
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setMinFunctionAlignment(2);
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// Handle operations that are handled in a similar way for all types.
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for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
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I <= MVT::LAST_FP_VALUETYPE;
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++I) {
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MVT VT = MVT::SimpleValueType(I);
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if (isTypeLegal(VT)) {
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// Expand SETCC(X, Y, COND) into SELECT_CC(X, Y, 1, 0, COND).
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setOperationAction(ISD::SETCC, VT, Expand);
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// Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
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setOperationAction(ISD::SELECT, VT, Expand);
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// Lower SELECT_CC and BR_CC into separate comparisons and branches.
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setOperationAction(ISD::SELECT_CC, VT, Custom);
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setOperationAction(ISD::BR_CC, VT, Custom);
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}
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}
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// Expand jump table branches as address arithmetic followed by an
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// indirect jump.
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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// Expand BRCOND into a BR_CC (see above).
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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// Handle integer types.
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for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
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I <= MVT::LAST_INTEGER_VALUETYPE;
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++I) {
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MVT VT = MVT::SimpleValueType(I);
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if (isTypeLegal(VT)) {
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// Expand individual DIV and REMs into DIVREMs.
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setOperationAction(ISD::SDIV, VT, Expand);
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setOperationAction(ISD::UDIV, VT, Expand);
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setOperationAction(ISD::SREM, VT, Expand);
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setOperationAction(ISD::UREM, VT, Expand);
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setOperationAction(ISD::SDIVREM, VT, Custom);
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setOperationAction(ISD::UDIVREM, VT, Custom);
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// Expand ATOMIC_LOAD and ATOMIC_STORE using ATOMIC_CMP_SWAP.
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// FIXME: probably much too conservative.
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setOperationAction(ISD::ATOMIC_LOAD, VT, Expand);
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setOperationAction(ISD::ATOMIC_STORE, VT, Expand);
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// No special instructions for these.
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setOperationAction(ISD::CTPOP, VT, Expand);
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setOperationAction(ISD::CTTZ, VT, Expand);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
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setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
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setOperationAction(ISD::ROTR, VT, Expand);
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// Use *MUL_LOHI where possible and a wider multiplication otherwise.
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setOperationAction(ISD::MULHS, VT, Expand);
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setOperationAction(ISD::MULHU, VT, Expand);
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// We have instructions for signed but not unsigned FP conversion.
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setOperationAction(ISD::FP_TO_UINT, VT, Expand);
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}
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}
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// Type legalization will convert 8- and 16-bit atomic operations into
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// forms that operate on i32s (but still keeping the original memory VT).
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// Lower them into full i32 operations.
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setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
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// We have instructions for signed but not unsigned FP conversion.
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// Handle unsigned 32-bit types as signed 64-bit types.
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
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// We have native support for a 64-bit CTLZ, via FLOGR.
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setOperationAction(ISD::CTLZ, MVT::i32, Promote);
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setOperationAction(ISD::CTLZ, MVT::i64, Legal);
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// Give LowerOperation the chance to replace 64-bit ORs with subregs.
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setOperationAction(ISD::OR, MVT::i64, Custom);
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// The architecture has 32-bit SMUL_LOHI and UMUL_LOHI (MR and MLR),
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// but they aren't really worth using. There is no 64-bit SMUL_LOHI,
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// but there is a 64-bit UMUL_LOHI: MLGR.
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
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// FIXME: Can we support these natively?
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setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
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// We have native instructions for i8, i16 and i32 extensions, but not i1.
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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// Handle the various types of symbolic address.
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setOperationAction(ISD::ConstantPool, PtrVT, Custom);
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setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
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setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
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setOperationAction(ISD::BlockAddress, PtrVT, Custom);
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setOperationAction(ISD::JumpTable, PtrVT, Custom);
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// We need to handle dynamic allocations specially because of the
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// 160-byte area at the bottom of the stack.
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setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
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// Use custom expanders so that we can force the function to use
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// a frame pointer.
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setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
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// Expand these using getExceptionSelectorRegister() and
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// getExceptionPointerRegister().
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setOperationAction(ISD::EXCEPTIONADDR, PtrVT, Expand);
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setOperationAction(ISD::EHSELECTION, PtrVT, Expand);
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// Handle floating-point types.
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for (unsigned I = MVT::FIRST_FP_VALUETYPE;
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I <= MVT::LAST_FP_VALUETYPE;
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++I) {
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MVT VT = MVT::SimpleValueType(I);
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if (isTypeLegal(VT)) {
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// We can use FI for FRINT.
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setOperationAction(ISD::FRINT, VT, Legal);
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// No special instructions for these.
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setOperationAction(ISD::FSIN, VT, Expand);
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setOperationAction(ISD::FCOS, VT, Expand);
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setOperationAction(ISD::FREM, VT, Expand);
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}
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}
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// We have fused multiply-addition for f32 and f64 but not f128.
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setOperationAction(ISD::FMA, MVT::f32, Legal);
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setOperationAction(ISD::FMA, MVT::f64, Legal);
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setOperationAction(ISD::FMA, MVT::f128, Expand);
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// Needed so that we don't try to implement f128 constant loads using
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// a load-and-extend of a f80 constant (in cases where the constant
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// would fit in an f80).
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setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
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// Floating-point truncation and stores need to be done separately.
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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setTruncStoreAction(MVT::f128, MVT::f32, Expand);
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setTruncStoreAction(MVT::f128, MVT::f64, Expand);
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// We have 64-bit FPR<->GPR moves, but need special handling for
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// 32-bit forms.
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setOperationAction(ISD::BITCAST, MVT::i32, Custom);
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setOperationAction(ISD::BITCAST, MVT::f32, Custom);
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// VASTART and VACOPY need to deal with the SystemZ-specific varargs
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// structure, but VAEND is a no-op.
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::VACOPY, MVT::Other, Custom);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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}
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bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
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// We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
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return Imm.isZero() || Imm.isNegZero();
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}
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bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
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bool *Fast) const {
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// Unaligned accesses should never be slower than the expanded version.
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// We check specifically for aligned accesses in the few cases where
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// they are required.
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if (Fast)
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*Fast = true;
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return true;
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}
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//===----------------------------------------------------------------------===//
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// Inline asm support
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//===----------------------------------------------------------------------===//
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TargetLowering::ConstraintType
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SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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case 'a': // Address register
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case 'd': // Data register (equivalent to 'r')
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case 'f': // Floating-point register
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case 'r': // General-purpose register
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return C_RegisterClass;
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case 'Q': // Memory with base and unsigned 12-bit displacement
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case 'R': // Likewise, plus an index
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case 'S': // Memory with base and signed 20-bit displacement
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case 'T': // Likewise, plus an index
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case 'm': // Equivalent to 'T'.
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return C_Memory;
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case 'I': // Unsigned 8-bit constant
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case 'J': // Unsigned 12-bit constant
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case 'K': // Signed 16-bit constant
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case 'L': // Signed 20-bit displacement (on all targets we support)
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case 'M': // 0x7fffffff
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return C_Other;
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default:
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break;
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}
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}
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return TargetLowering::getConstraintType(Constraint);
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}
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TargetLowering::ConstraintWeight SystemZTargetLowering::
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getSingleConstraintMatchWeight(AsmOperandInfo &info,
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const char *constraint) const {
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ConstraintWeight weight = CW_Invalid;
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Value *CallOperandVal = info.CallOperandVal;
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// If we don't have a value, we can't do a match,
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// but allow it at the lowest weight.
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if (CallOperandVal == NULL)
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return CW_Default;
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Type *type = CallOperandVal->getType();
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// Look at the constraint type.
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switch (*constraint) {
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default:
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weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
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break;
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case 'a': // Address register
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case 'd': // Data register (equivalent to 'r')
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case 'r': // General-purpose register
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if (CallOperandVal->getType()->isIntegerTy())
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weight = CW_Register;
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break;
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case 'f': // Floating-point register
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if (type->isFloatingPointTy())
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weight = CW_Register;
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break;
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case 'I': // Unsigned 8-bit constant
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if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
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if (isUInt<8>(C->getZExtValue()))
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weight = CW_Constant;
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break;
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case 'J': // Unsigned 12-bit constant
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if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
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if (isUInt<12>(C->getZExtValue()))
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weight = CW_Constant;
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break;
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case 'K': // Signed 16-bit constant
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if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
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if (isInt<16>(C->getSExtValue()))
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weight = CW_Constant;
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break;
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case 'L': // Signed 20-bit displacement (on all targets we support)
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if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
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if (isInt<20>(C->getSExtValue()))
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weight = CW_Constant;
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break;
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case 'M': // 0x7fffffff
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if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
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if (C->getZExtValue() == 0x7fffffff)
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weight = CW_Constant;
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break;
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}
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return weight;
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}
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std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
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getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
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if (Constraint.size() == 1) {
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// GCC Constraint Letters
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switch (Constraint[0]) {
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default: break;
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case 'd': // Data register (equivalent to 'r')
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case 'r': // General-purpose register
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if (VT == MVT::i64)
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return std::make_pair(0U, &SystemZ::GR64BitRegClass);
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else if (VT == MVT::i128)
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return std::make_pair(0U, &SystemZ::GR128BitRegClass);
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return std::make_pair(0U, &SystemZ::GR32BitRegClass);
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case 'a': // Address register
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if (VT == MVT::i64)
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return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
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else if (VT == MVT::i128)
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return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
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return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
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case 'f': // Floating-point register
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if (VT == MVT::f64)
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return std::make_pair(0U, &SystemZ::FP64BitRegClass);
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else if (VT == MVT::f128)
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return std::make_pair(0U, &SystemZ::FP128BitRegClass);
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return std::make_pair(0U, &SystemZ::FP32BitRegClass);
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}
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}
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return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
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}
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void SystemZTargetLowering::
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LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const {
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// Only support length 1 constraints for now.
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if (Constraint.length() == 1) {
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switch (Constraint[0]) {
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case 'I': // Unsigned 8-bit constant
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
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if (isUInt<8>(C->getZExtValue()))
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Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
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Op.getValueType()));
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return;
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case 'J': // Unsigned 12-bit constant
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
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if (isUInt<12>(C->getZExtValue()))
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Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
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Op.getValueType()));
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return;
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case 'K': // Signed 16-bit constant
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
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if (isInt<16>(C->getSExtValue()))
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Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
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Op.getValueType()));
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return;
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case 'L': // Signed 20-bit displacement (on all targets we support)
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
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if (isInt<20>(C->getSExtValue()))
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Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
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Op.getValueType()));
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return;
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case 'M': // 0x7fffffff
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
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if (C->getZExtValue() == 0x7fffffff)
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Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
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Op.getValueType()));
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return;
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}
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}
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TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
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}
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//===----------------------------------------------------------------------===//
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// Calling conventions
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//===----------------------------------------------------------------------===//
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#include "SystemZGenCallingConv.inc"
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// Value is a value that has been passed to us in the location described by VA
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// (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
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// any loads onto Chain.
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static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
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CCValAssign &VA, SDValue Chain,
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SDValue Value) {
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// If the argument has been promoted from a smaller type, insert an
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// assertion to capture this.
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if (VA.getLocInfo() == CCValAssign::SExt)
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Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
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DAG.getValueType(VA.getValVT()));
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if (VA.isExtInLoc())
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Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
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else if (VA.getLocInfo() == CCValAssign::Indirect)
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Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
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MachinePointerInfo(), false, false, false, 0);
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else
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assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
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return Value;
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}
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// Value is a value of type VA.getValVT() that we need to copy into
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// the location described by VA. Return a copy of Value converted to
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// VA.getValVT(). The caller is responsible for handling indirect values.
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static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
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CCValAssign &VA, SDValue Value) {
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switch (VA.getLocInfo()) {
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case CCValAssign::SExt:
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return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
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case CCValAssign::ZExt:
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return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
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case CCValAssign::AExt:
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return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
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case CCValAssign::Full:
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return Value;
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default:
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llvm_unreachable("Unhandled getLocInfo()");
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}
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}
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SDValue SystemZTargetLowering::
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LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SDLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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SystemZMachineFunctionInfo *FuncInfo =
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MF.getInfo<SystemZMachineFunctionInfo>();
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const SystemZFrameLowering *TFL =
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static_cast<const SystemZFrameLowering *>(TM.getFrameLowering());
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
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unsigned NumFixedGPRs = 0;
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unsigned NumFixedFPRs = 0;
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for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
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SDValue ArgValue;
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CCValAssign &VA = ArgLocs[I];
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EVT LocVT = VA.getLocVT();
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if (VA.isRegLoc()) {
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// Arguments passed in registers
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const TargetRegisterClass *RC;
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switch (LocVT.getSimpleVT().SimpleTy) {
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default:
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// Integers smaller than i64 should be promoted to i64.
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llvm_unreachable("Unexpected argument type");
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case MVT::i32:
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NumFixedGPRs += 1;
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RC = &SystemZ::GR32BitRegClass;
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break;
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case MVT::i64:
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NumFixedGPRs += 1;
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RC = &SystemZ::GR64BitRegClass;
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break;
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case MVT::f32:
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NumFixedFPRs += 1;
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RC = &SystemZ::FP32BitRegClass;
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break;
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case MVT::f64:
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NumFixedFPRs += 1;
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RC = &SystemZ::FP64BitRegClass;
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break;
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}
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unsigned VReg = MRI.createVirtualRegister(RC);
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MRI.addLiveIn(VA.getLocReg(), VReg);
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ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
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} else {
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assert(VA.isMemLoc() && "Argument not register or memory");
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// Create the frame index object for this incoming parameter.
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int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
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VA.getLocMemOffset(), true);
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// Create the SelectionDAG nodes corresponding to a load
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// from this parameter. Unpromoted ints and floats are
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// passed as right-justified 8-byte values.
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EVT PtrVT = getPointerTy();
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SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
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if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
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FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
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ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
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MachinePointerInfo::getFixedStack(FI),
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false, false, false, 0);
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}
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// Convert the value of the argument register into the value that's
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// being passed.
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InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
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}
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if (IsVarArg) {
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// Save the number of non-varargs registers for later use by va_start, etc.
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FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
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FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
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// Likewise the address (in the form of a frame index) of where the
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// first stack vararg would be. The 1-byte size here is arbitrary.
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int64_t StackSize = CCInfo.getNextStackOffset();
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FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
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// ...and a similar frame index for the caller-allocated save area
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// that will be used to store the incoming registers.
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int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
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unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
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FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
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// Store the FPR varargs in the reserved frame slots. (We store the
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// GPRs as part of the prologue.)
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if (NumFixedFPRs < SystemZ::NumArgFPRs) {
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SDValue MemOps[SystemZ::NumArgFPRs];
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for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
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unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
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int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
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SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
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unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
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&SystemZ::FP64BitRegClass);
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SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
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MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
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MachinePointerInfo::getFixedStack(FI),
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false, false, 0);
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}
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// Join the stores, which are independent of one another.
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Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
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&MemOps[NumFixedFPRs],
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SystemZ::NumArgFPRs - NumFixedFPRs);
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}
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}
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return Chain;
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}
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SDValue
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SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const {
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SelectionDAG &DAG = CLI.DAG;
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SDLoc &DL = CLI.DL;
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SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
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SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
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SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
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SDValue Chain = CLI.Chain;
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SDValue Callee = CLI.Callee;
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bool &isTailCall = CLI.IsTailCall;
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CallingConv::ID CallConv = CLI.CallConv;
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bool IsVarArg = CLI.IsVarArg;
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MachineFunction &MF = DAG.getMachineFunction();
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EVT PtrVT = getPointerTy();
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// SystemZ target does not yet support tail call optimization.
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isTailCall = false;
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// Analyze the operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
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ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = ArgCCInfo.getNextStackOffset();
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// Mark the start of the call.
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
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DL);
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// Copy argument values to their designated locations.
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SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
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SmallVector<SDValue, 8> MemOpChains;
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SDValue StackPtr;
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for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
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CCValAssign &VA = ArgLocs[I];
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SDValue ArgValue = OutVals[I];
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if (VA.getLocInfo() == CCValAssign::Indirect) {
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// Store the argument in a stack slot and pass its address.
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SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
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int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
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MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
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MachinePointerInfo::getFixedStack(FI),
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false, false, 0));
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ArgValue = SpillSlot;
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} else
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ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
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if (VA.isRegLoc())
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// Queue up the argument copies and emit them at the end.
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
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else {
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assert(VA.isMemLoc() && "Argument not register or memory");
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// Work out the address of the stack slot. Unpromoted ints and
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// floats are passed as right-justified 8-byte values.
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if (!StackPtr.getNode())
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StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
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unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
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if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
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Offset += 4;
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SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
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DAG.getIntPtrConstant(Offset));
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// Emit the store.
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MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
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MachinePointerInfo(),
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false, false, 0));
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}
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}
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// Join the stores, which are independent of one another.
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of copy-to-reg nodes, chained and glued together.
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SDValue Glue;
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for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
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Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
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RegsToPass[I].second, Glue);
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Glue = Chain.getValue(1);
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}
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// Accept direct calls by converting symbolic call addresses to the
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// associated Target* opcodes.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
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Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
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} else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
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Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
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Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
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}
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// The first call operand is the chain and the second is the target address.
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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// Add argument registers to the end of the list so that they are
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// known live into the call.
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for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
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Ops.push_back(DAG.getRegister(RegsToPass[I].first,
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RegsToPass[I].second.getValueType()));
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// Glue the call to the argument copies, if any.
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if (Glue.getNode())
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Ops.push_back(Glue);
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// Emit the call.
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
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Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
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Glue = Chain.getValue(1);
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// Mark the end of the call, which is glued to the call itself.
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Chain = DAG.getCALLSEQ_END(Chain,
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DAG.getConstant(NumBytes, PtrVT, true),
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DAG.getConstant(0, PtrVT, true),
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Glue, DL);
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Glue = Chain.getValue(1);
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// Assign locations to each value returned by this call.
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SmallVector<CCValAssign, 16> RetLocs;
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CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
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RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
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// Copy all of the result registers out of their specified physreg.
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for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
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CCValAssign &VA = RetLocs[I];
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// Copy the value out, gluing the copy to the end of the call sequence.
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SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
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VA.getLocVT(), Glue);
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Chain = RetValue.getValue(1);
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Glue = RetValue.getValue(2);
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// Convert the value of the return register into the value that's
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// being returned.
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InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
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}
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return Chain;
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}
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SDValue
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SystemZTargetLowering::LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc DL, SelectionDAG &DAG) const {
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MachineFunction &MF = DAG.getMachineFunction();
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// Assign locations to each returned value.
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SmallVector<CCValAssign, 16> RetLocs;
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CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
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RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
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// Quick exit for void returns
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if (RetLocs.empty())
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return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
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// Copy the result values into the output registers.
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SDValue Glue;
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SmallVector<SDValue, 4> RetOps;
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RetOps.push_back(Chain);
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for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
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CCValAssign &VA = RetLocs[I];
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SDValue RetValue = OutVals[I];
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// Make the return register live on exit.
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assert(VA.isRegLoc() && "Can only return in registers!");
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// Promote the value as required.
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RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
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// Chain and glue the copies together.
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unsigned Reg = VA.getLocReg();
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Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
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Glue = Chain.getValue(1);
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RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
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}
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// Update chain and glue.
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RetOps[0] = Chain;
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if (Glue.getNode())
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RetOps.push_back(Glue);
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return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other,
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RetOps.data(), RetOps.size());
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}
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// CC is a comparison that will be implemented using an integer or
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// floating-point comparison. Return the condition code mask for
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// a branch on true. In the integer case, CCMASK_CMP_UO is set for
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// unsigned comparisons and clear for signed ones. In the floating-point
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// case, CCMASK_CMP_UO has its normal mask meaning (unordered).
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static unsigned CCMaskForCondCode(ISD::CondCode CC) {
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#define CONV(X) \
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case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
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case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
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case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
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switch (CC) {
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default:
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llvm_unreachable("Invalid integer condition!");
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CONV(EQ);
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CONV(NE);
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CONV(GT);
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CONV(GE);
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CONV(LT);
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CONV(LE);
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case ISD::SETO: return SystemZ::CCMASK_CMP_O;
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case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
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}
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#undef CONV
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}
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// If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
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// is suitable for CLI(Y), CHHSI or CLHHSI, adjust the operands as necessary.
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static void adjustSubwordCmp(SelectionDAG &DAG, bool &IsUnsigned,
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SDValue &CmpOp0, SDValue &CmpOp1,
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unsigned &CCMask) {
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// For us to make any changes, it must a comparison between a single-use
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// load and a constant.
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if (!CmpOp0.hasOneUse() ||
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CmpOp0.getOpcode() != ISD::LOAD ||
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CmpOp1.getOpcode() != ISD::Constant)
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return;
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// We must have an 8- or 16-bit load.
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LoadSDNode *Load = cast<LoadSDNode>(CmpOp0);
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unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
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if (NumBits != 8 && NumBits != 16)
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return;
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// The load must be an extending one and the constant must be within the
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// range of the unextended value.
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ConstantSDNode *Constant = cast<ConstantSDNode>(CmpOp1);
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uint64_t Value = Constant->getZExtValue();
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uint64_t Mask = (1 << NumBits) - 1;
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if (Load->getExtensionType() == ISD::SEXTLOAD) {
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int64_t SignedValue = Constant->getSExtValue();
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if (uint64_t(SignedValue) + (1ULL << (NumBits - 1)) > Mask)
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return;
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// Unsigned comparison between two sign-extended values is equivalent
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// to unsigned comparison between two zero-extended values.
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if (IsUnsigned)
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Value &= Mask;
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else if (CCMask == SystemZ::CCMASK_CMP_EQ ||
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CCMask == SystemZ::CCMASK_CMP_NE)
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// Any choice of IsUnsigned is OK for equality comparisons.
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// We could use either CHHSI or CLHHSI for 16-bit comparisons,
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// but since we use CLHHSI for zero extensions, it seems better
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// to be consistent and do the same here.
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Value &= Mask, IsUnsigned = true;
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else if (NumBits == 8) {
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// Try to treat the comparison as unsigned, so that we can use CLI.
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// Adjust CCMask and Value as necessary.
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if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_LT)
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// Test whether the high bit of the byte is set.
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Value = 127, CCMask = SystemZ::CCMASK_CMP_GT, IsUnsigned = true;
|
|
else if (SignedValue == -1 && CCMask == SystemZ::CCMASK_CMP_GT)
|
|
// Test whether the high bit of the byte is clear.
|
|
Value = 128, CCMask = SystemZ::CCMASK_CMP_LT, IsUnsigned = true;
|
|
else
|
|
// No instruction exists for this combination.
|
|
return;
|
|
}
|
|
} else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
|
|
if (Value > Mask)
|
|
return;
|
|
// Signed comparison between two zero-extended values is equivalent
|
|
// to unsigned comparison.
|
|
IsUnsigned = true;
|
|
} else
|
|
return;
|
|
|
|
// Make sure that the first operand is an i32 of the right extension type.
|
|
ISD::LoadExtType ExtType = IsUnsigned ? ISD::ZEXTLOAD : ISD::SEXTLOAD;
|
|
if (CmpOp0.getValueType() != MVT::i32 ||
|
|
Load->getExtensionType() != ExtType)
|
|
CmpOp0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
|
|
Load->getChain(), Load->getBasePtr(),
|
|
Load->getPointerInfo(), Load->getMemoryVT(),
|
|
Load->isVolatile(), Load->isNonTemporal(),
|
|
Load->getAlignment());
|
|
|
|
// Make sure that the second operand is an i32 with the right value.
|
|
if (CmpOp1.getValueType() != MVT::i32 ||
|
|
Value != Constant->getZExtValue())
|
|
CmpOp1 = DAG.getConstant(Value, MVT::i32);
|
|
}
|
|
|
|
// Return true if a comparison described by CCMask, CmpOp0 and CmpOp1
|
|
// is an equality comparison that is better implemented using unsigned
|
|
// rather than signed comparison instructions.
|
|
static bool preferUnsignedComparison(SelectionDAG &DAG, SDValue CmpOp0,
|
|
SDValue CmpOp1, unsigned CCMask) {
|
|
// The test must be for equality or inequality.
|
|
if (CCMask != SystemZ::CCMASK_CMP_EQ && CCMask != SystemZ::CCMASK_CMP_NE)
|
|
return false;
|
|
|
|
if (CmpOp1.getOpcode() == ISD::Constant) {
|
|
uint64_t Value = cast<ConstantSDNode>(CmpOp1)->getSExtValue();
|
|
|
|
// If we're comparing with memory, prefer unsigned comparisons for
|
|
// values that are in the unsigned 16-bit range but not the signed
|
|
// 16-bit range. We want to use CLFHSI and CLGHSI.
|
|
if (CmpOp0.hasOneUse() &&
|
|
ISD::isNormalLoad(CmpOp0.getNode()) &&
|
|
(Value >= 32768 && Value < 65536))
|
|
return true;
|
|
|
|
// Use unsigned comparisons for values that are in the CLGFI range
|
|
// but not in the CGFI range.
|
|
if (CmpOp0.getValueType() == MVT::i64 && (Value >> 31) == 1)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
// Prefer CL for zero-extended loads.
|
|
if (CmpOp1.getOpcode() == ISD::ZERO_EXTEND ||
|
|
ISD::isZEXTLoad(CmpOp1.getNode()))
|
|
return true;
|
|
|
|
// ...and for "in-register" zero extensions.
|
|
if (CmpOp1.getOpcode() == ISD::AND && CmpOp1.getValueType() == MVT::i64) {
|
|
SDValue Mask = CmpOp1.getOperand(1);
|
|
if (Mask.getOpcode() == ISD::Constant &&
|
|
cast<ConstantSDNode>(Mask)->getZExtValue() == 0xffffffff)
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
// Return a target node that compares CmpOp0 and CmpOp1. Set CCMask to the
|
|
// 4-bit condition-code mask for CC.
|
|
static SDValue emitCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
|
|
ISD::CondCode CC, unsigned &CCMask) {
|
|
bool IsUnsigned = false;
|
|
CCMask = CCMaskForCondCode(CC);
|
|
if (!CmpOp0.getValueType().isFloatingPoint()) {
|
|
IsUnsigned = CCMask & SystemZ::CCMASK_CMP_UO;
|
|
CCMask &= ~SystemZ::CCMASK_CMP_UO;
|
|
adjustSubwordCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
|
|
if (preferUnsignedComparison(DAG, CmpOp0, CmpOp1, CCMask))
|
|
IsUnsigned = true;
|
|
}
|
|
|
|
SDLoc DL(CmpOp0);
|
|
return DAG.getNode((IsUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
|
|
DL, MVT::Glue, CmpOp0, CmpOp1);
|
|
}
|
|
|
|
// Lower a binary operation that produces two VT results, one in each
|
|
// half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
|
|
// Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
|
|
// on the extended Op0 and (unextended) Op1. Store the even register result
|
|
// in Even and the odd register result in Odd.
|
|
static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
|
|
unsigned Extend, unsigned Opcode,
|
|
SDValue Op0, SDValue Op1,
|
|
SDValue &Even, SDValue &Odd) {
|
|
SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
|
|
SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
|
|
SDValue(In128, 0), Op1);
|
|
bool Is32Bit = is32Bit(VT);
|
|
SDValue SubReg0 = DAG.getTargetConstant(SystemZ::even128(Is32Bit), VT);
|
|
SDValue SubReg1 = DAG.getTargetConstant(SystemZ::odd128(Is32Bit), VT);
|
|
SDNode *Reg0 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
|
|
VT, Result, SubReg0);
|
|
SDNode *Reg1 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
|
|
VT, Result, SubReg1);
|
|
Even = SDValue(Reg0, 0);
|
|
Odd = SDValue(Reg1, 0);
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
|
|
SDValue Chain = Op.getOperand(0);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
|
|
SDValue CmpOp0 = Op.getOperand(2);
|
|
SDValue CmpOp1 = Op.getOperand(3);
|
|
SDValue Dest = Op.getOperand(4);
|
|
SDLoc DL(Op);
|
|
|
|
unsigned CCMask;
|
|
SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCMask);
|
|
return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
|
|
Chain, DAG.getConstant(CCMask, MVT::i32), Dest, Flags);
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
SDValue CmpOp0 = Op.getOperand(0);
|
|
SDValue CmpOp1 = Op.getOperand(1);
|
|
SDValue TrueOp = Op.getOperand(2);
|
|
SDValue FalseOp = Op.getOperand(3);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
|
|
SDLoc DL(Op);
|
|
|
|
unsigned CCMask;
|
|
SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCMask);
|
|
|
|
SmallVector<SDValue, 4> Ops;
|
|
Ops.push_back(TrueOp);
|
|
Ops.push_back(FalseOp);
|
|
Ops.push_back(DAG.getConstant(CCMask, MVT::i32));
|
|
Ops.push_back(Flags);
|
|
|
|
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
|
|
return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, &Ops[0], Ops.size());
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
|
|
SelectionDAG &DAG) const {
|
|
SDLoc DL(Node);
|
|
const GlobalValue *GV = Node->getGlobal();
|
|
int64_t Offset = Node->getOffset();
|
|
EVT PtrVT = getPointerTy();
|
|
Reloc::Model RM = TM.getRelocationModel();
|
|
CodeModel::Model CM = TM.getCodeModel();
|
|
|
|
SDValue Result;
|
|
if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
|
|
// Make sure that the offset is aligned to a halfword. If it isn't,
|
|
// create an "anchor" at the previous 12-bit boundary.
|
|
// FIXME check whether there is a better way of handling this.
|
|
if (Offset & 1) {
|
|
Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
|
|
Offset & ~uint64_t(0xfff));
|
|
Offset &= 0xfff;
|
|
} else {
|
|
Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Offset);
|
|
Offset = 0;
|
|
}
|
|
Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
|
|
} else {
|
|
Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
|
|
Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
|
|
Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
|
|
MachinePointerInfo::getGOT(), false, false, false, 0);
|
|
}
|
|
|
|
// If there was a non-zero offset that we didn't fold, create an explicit
|
|
// addition for it.
|
|
if (Offset != 0)
|
|
Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
|
|
DAG.getConstant(Offset, PtrVT));
|
|
|
|
return Result;
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
|
|
SelectionDAG &DAG) const {
|
|
SDLoc DL(Node);
|
|
const GlobalValue *GV = Node->getGlobal();
|
|
EVT PtrVT = getPointerTy();
|
|
TLSModel::Model model = TM.getTLSModel(GV);
|
|
|
|
if (model != TLSModel::LocalExec)
|
|
llvm_unreachable("only local-exec TLS mode supported");
|
|
|
|
// The high part of the thread pointer is in access register 0.
|
|
SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
|
|
DAG.getConstant(0, MVT::i32));
|
|
TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
|
|
|
|
// The low part of the thread pointer is in access register 1.
|
|
SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
|
|
DAG.getConstant(1, MVT::i32));
|
|
TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
|
|
|
|
// Merge them into a single 64-bit address.
|
|
SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
|
|
DAG.getConstant(32, PtrVT));
|
|
SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
|
|
|
|
// Get the offset of GA from the thread pointer.
|
|
SystemZConstantPoolValue *CPV =
|
|
SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
|
|
|
|
// Force the offset into the constant pool and load it from there.
|
|
SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
|
|
SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
|
|
CPAddr, MachinePointerInfo::getConstantPool(),
|
|
false, false, false, 0);
|
|
|
|
// Add the base and offset together.
|
|
return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
|
|
SelectionDAG &DAG) const {
|
|
SDLoc DL(Node);
|
|
const BlockAddress *BA = Node->getBlockAddress();
|
|
int64_t Offset = Node->getOffset();
|
|
EVT PtrVT = getPointerTy();
|
|
|
|
SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
|
|
Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
|
|
return Result;
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
|
|
SelectionDAG &DAG) const {
|
|
SDLoc DL(JT);
|
|
EVT PtrVT = getPointerTy();
|
|
SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
|
|
|
|
// Use LARL to load the address of the table.
|
|
return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
|
|
SelectionDAG &DAG) const {
|
|
SDLoc DL(CP);
|
|
EVT PtrVT = getPointerTy();
|
|
|
|
SDValue Result;
|
|
if (CP->isMachineConstantPoolEntry())
|
|
Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
|
|
CP->getAlignment());
|
|
else
|
|
Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
|
|
CP->getAlignment(), CP->getOffset());
|
|
|
|
// Use LARL to load the address of the constant pool entry.
|
|
return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
SDLoc DL(Op);
|
|
SDValue In = Op.getOperand(0);
|
|
EVT InVT = In.getValueType();
|
|
EVT ResVT = Op.getValueType();
|
|
|
|
SDValue SubReg32 = DAG.getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
|
|
SDValue Shift32 = DAG.getConstant(32, MVT::i64);
|
|
if (InVT == MVT::i32 && ResVT == MVT::f32) {
|
|
SDValue In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
|
|
SDValue Shift = DAG.getNode(ISD::SHL, DL, MVT::i64, In64, Shift32);
|
|
SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, Shift);
|
|
SDNode *Out = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
|
|
MVT::f32, Out64, SubReg32);
|
|
return SDValue(Out, 0);
|
|
}
|
|
if (InVT == MVT::f32 && ResVT == MVT::i32) {
|
|
SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
|
|
SDNode *In64 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
|
|
MVT::f64, SDValue(U64, 0), In, SubReg32);
|
|
SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, SDValue(In64, 0));
|
|
SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64, Shift32);
|
|
SDValue Out = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
|
|
return Out;
|
|
}
|
|
llvm_unreachable("Unexpected bitcast combination");
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
SystemZMachineFunctionInfo *FuncInfo =
|
|
MF.getInfo<SystemZMachineFunctionInfo>();
|
|
EVT PtrVT = getPointerTy();
|
|
|
|
SDValue Chain = Op.getOperand(0);
|
|
SDValue Addr = Op.getOperand(1);
|
|
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
|
SDLoc DL(Op);
|
|
|
|
// The initial values of each field.
|
|
const unsigned NumFields = 4;
|
|
SDValue Fields[NumFields] = {
|
|
DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
|
|
DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
|
|
DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
|
|
DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
|
|
};
|
|
|
|
// Store each field into its respective slot.
|
|
SDValue MemOps[NumFields];
|
|
unsigned Offset = 0;
|
|
for (unsigned I = 0; I < NumFields; ++I) {
|
|
SDValue FieldAddr = Addr;
|
|
if (Offset != 0)
|
|
FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
|
|
DAG.getIntPtrConstant(Offset));
|
|
MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
|
|
MachinePointerInfo(SV, Offset),
|
|
false, false, 0);
|
|
Offset += 8;
|
|
}
|
|
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps, NumFields);
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
SDValue Chain = Op.getOperand(0);
|
|
SDValue DstPtr = Op.getOperand(1);
|
|
SDValue SrcPtr = Op.getOperand(2);
|
|
const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
|
|
const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
|
|
SDLoc DL(Op);
|
|
|
|
return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
|
|
/*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
|
|
MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::
|
|
lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
|
|
SDValue Chain = Op.getOperand(0);
|
|
SDValue Size = Op.getOperand(1);
|
|
SDLoc DL(Op);
|
|
|
|
unsigned SPReg = getStackPointerRegisterToSaveRestore();
|
|
|
|
// Get a reference to the stack pointer.
|
|
SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
|
|
|
|
// Get the new stack pointer value.
|
|
SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
|
|
|
|
// Copy the new stack pointer back.
|
|
Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
|
|
|
|
// The allocated data lives above the 160 bytes allocated for the standard
|
|
// frame, plus any outgoing stack arguments. We don't know how much that
|
|
// amounts to yet, so emit a special ADJDYNALLOC placeholder.
|
|
SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
|
|
SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
|
|
|
|
SDValue Ops[2] = { Result, Chain };
|
|
return DAG.getMergeValues(Ops, 2, DL);
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
EVT VT = Op.getValueType();
|
|
SDLoc DL(Op);
|
|
assert(!is32Bit(VT) && "Only support 64-bit UMUL_LOHI");
|
|
|
|
// UMUL_LOHI64 returns the low result in the odd register and the high
|
|
// result in the even register. UMUL_LOHI is defined to return the
|
|
// low half first, so the results are in reverse order.
|
|
SDValue Ops[2];
|
|
lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
|
|
Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
|
|
return DAG.getMergeValues(Ops, 2, DL);
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
SDValue Op0 = Op.getOperand(0);
|
|
SDValue Op1 = Op.getOperand(1);
|
|
EVT VT = Op.getValueType();
|
|
SDLoc DL(Op);
|
|
|
|
// We use DSGF for 32-bit division.
|
|
if (is32Bit(VT)) {
|
|
Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
|
|
Op1 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op1);
|
|
}
|
|
|
|
// DSG(F) takes a 64-bit dividend, so the even register in the GR128
|
|
// input is "don't care". The instruction returns the remainder in
|
|
// the even register and the quotient in the odd register.
|
|
SDValue Ops[2];
|
|
lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::SDIVREM64,
|
|
Op0, Op1, Ops[1], Ops[0]);
|
|
return DAG.getMergeValues(Ops, 2, DL);
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
EVT VT = Op.getValueType();
|
|
SDLoc DL(Op);
|
|
|
|
// DL(G) uses a double-width dividend, so we need to clear the even
|
|
// register in the GR128 input. The instruction returns the remainder
|
|
// in the even register and the quotient in the odd register.
|
|
SDValue Ops[2];
|
|
if (is32Bit(VT))
|
|
lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
|
|
Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
|
|
else
|
|
lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
|
|
Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
|
|
return DAG.getMergeValues(Ops, 2, DL);
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
|
|
assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
|
|
|
|
// Get the known-zero masks for each operand.
|
|
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
|
|
APInt KnownZero[2], KnownOne[2];
|
|
DAG.ComputeMaskedBits(Ops[0], KnownZero[0], KnownOne[0]);
|
|
DAG.ComputeMaskedBits(Ops[1], KnownZero[1], KnownOne[1]);
|
|
|
|
// See if the upper 32 bits of one operand and the lower 32 bits of the
|
|
// other are known zero. They are the low and high operands respectively.
|
|
uint64_t Masks[] = { KnownZero[0].getZExtValue(),
|
|
KnownZero[1].getZExtValue() };
|
|
unsigned High, Low;
|
|
if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
|
|
High = 1, Low = 0;
|
|
else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
|
|
High = 0, Low = 1;
|
|
else
|
|
return Op;
|
|
|
|
SDValue LowOp = Ops[Low];
|
|
SDValue HighOp = Ops[High];
|
|
|
|
// If the high part is a constant, we're better off using IILH.
|
|
if (HighOp.getOpcode() == ISD::Constant)
|
|
return Op;
|
|
|
|
// If the low part is a constant that is outside the range of LHI,
|
|
// then we're better off using IILF.
|
|
if (LowOp.getOpcode() == ISD::Constant) {
|
|
int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
|
|
if (!isInt<16>(Value))
|
|
return Op;
|
|
}
|
|
|
|
// Check whether the high part is an AND that doesn't change the
|
|
// high 32 bits and just masks out low bits. We can skip it if so.
|
|
if (HighOp.getOpcode() == ISD::AND &&
|
|
HighOp.getOperand(1).getOpcode() == ISD::Constant) {
|
|
ConstantSDNode *MaskNode = cast<ConstantSDNode>(HighOp.getOperand(1));
|
|
uint64_t Mask = MaskNode->getZExtValue() | Masks[High];
|
|
if ((Mask >> 32) == 0xffffffff)
|
|
HighOp = HighOp.getOperand(0);
|
|
}
|
|
|
|
// Take advantage of the fact that all GR32 operations only change the
|
|
// low 32 bits by truncating Low to an i32 and inserting it directly
|
|
// using a subreg. The interesting cases are those where the truncation
|
|
// can be folded.
|
|
SDLoc DL(Op);
|
|
SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
|
|
SDValue SubReg32 = DAG.getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
|
|
SDNode *Result = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
|
|
MVT::i64, HighOp, Low32, SubReg32);
|
|
return SDValue(Result, 0);
|
|
}
|
|
|
|
// Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
|
|
// two into the fullword ATOMIC_LOADW_* operation given by Opcode.
|
|
SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
|
|
SelectionDAG &DAG,
|
|
unsigned Opcode) const {
|
|
AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
|
|
|
|
// 32-bit operations need no code outside the main loop.
|
|
EVT NarrowVT = Node->getMemoryVT();
|
|
EVT WideVT = MVT::i32;
|
|
if (NarrowVT == WideVT)
|
|
return Op;
|
|
|
|
int64_t BitSize = NarrowVT.getSizeInBits();
|
|
SDValue ChainIn = Node->getChain();
|
|
SDValue Addr = Node->getBasePtr();
|
|
SDValue Src2 = Node->getVal();
|
|
MachineMemOperand *MMO = Node->getMemOperand();
|
|
SDLoc DL(Node);
|
|
EVT PtrVT = Addr.getValueType();
|
|
|
|
// Convert atomic subtracts of constants into additions.
|
|
if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
|
|
if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Src2)) {
|
|
Opcode = SystemZISD::ATOMIC_LOADW_ADD;
|
|
Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
|
|
}
|
|
|
|
// Get the address of the containing word.
|
|
SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
|
|
DAG.getConstant(-4, PtrVT));
|
|
|
|
// Get the number of bits that the word must be rotated left in order
|
|
// to bring the field to the top bits of a GR32.
|
|
SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
|
|
DAG.getConstant(3, PtrVT));
|
|
BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
|
|
|
|
// Get the complementing shift amount, for rotating a field in the top
|
|
// bits back to its proper position.
|
|
SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
|
|
DAG.getConstant(0, WideVT), BitShift);
|
|
|
|
// Extend the source operand to 32 bits and prepare it for the inner loop.
|
|
// ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
|
|
// operations require the source to be shifted in advance. (This shift
|
|
// can be folded if the source is constant.) For AND and NAND, the lower
|
|
// bits must be set, while for other opcodes they should be left clear.
|
|
if (Opcode != SystemZISD::ATOMIC_SWAPW)
|
|
Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
|
|
DAG.getConstant(32 - BitSize, WideVT));
|
|
if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
|
|
Opcode == SystemZISD::ATOMIC_LOADW_NAND)
|
|
Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
|
|
DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
|
|
|
|
// Construct the ATOMIC_LOADW_* node.
|
|
SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
|
|
SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
|
|
DAG.getConstant(BitSize, WideVT) };
|
|
SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
|
|
array_lengthof(Ops),
|
|
NarrowVT, MMO);
|
|
|
|
// Rotate the result of the final CS so that the field is in the lower
|
|
// bits of a GR32, then truncate it.
|
|
SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
|
|
DAG.getConstant(BitSize, WideVT));
|
|
SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
|
|
|
|
SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
|
|
return DAG.getMergeValues(RetOps, 2, DL);
|
|
}
|
|
|
|
// Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
|
|
// into a fullword ATOMIC_CMP_SWAPW operation.
|
|
SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
|
|
|
|
// We have native support for 32-bit compare and swap.
|
|
EVT NarrowVT = Node->getMemoryVT();
|
|
EVT WideVT = MVT::i32;
|
|
if (NarrowVT == WideVT)
|
|
return Op;
|
|
|
|
int64_t BitSize = NarrowVT.getSizeInBits();
|
|
SDValue ChainIn = Node->getOperand(0);
|
|
SDValue Addr = Node->getOperand(1);
|
|
SDValue CmpVal = Node->getOperand(2);
|
|
SDValue SwapVal = Node->getOperand(3);
|
|
MachineMemOperand *MMO = Node->getMemOperand();
|
|
SDLoc DL(Node);
|
|
EVT PtrVT = Addr.getValueType();
|
|
|
|
// Get the address of the containing word.
|
|
SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
|
|
DAG.getConstant(-4, PtrVT));
|
|
|
|
// Get the number of bits that the word must be rotated left in order
|
|
// to bring the field to the top bits of a GR32.
|
|
SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
|
|
DAG.getConstant(3, PtrVT));
|
|
BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
|
|
|
|
// Get the complementing shift amount, for rotating a field in the top
|
|
// bits back to its proper position.
|
|
SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
|
|
DAG.getConstant(0, WideVT), BitShift);
|
|
|
|
// Construct the ATOMIC_CMP_SWAPW node.
|
|
SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
|
|
SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
|
|
NegBitShift, DAG.getConstant(BitSize, WideVT) };
|
|
SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
|
|
VTList, Ops, array_lengthof(Ops),
|
|
NarrowVT, MMO);
|
|
return AtomicOp;
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
|
|
return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
|
|
SystemZ::R15D, Op.getValueType());
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
|
|
return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
|
|
SystemZ::R15D, Op.getOperand(1));
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
switch (Op.getOpcode()) {
|
|
case ISD::BR_CC:
|
|
return lowerBR_CC(Op, DAG);
|
|
case ISD::SELECT_CC:
|
|
return lowerSELECT_CC(Op, DAG);
|
|
case ISD::GlobalAddress:
|
|
return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
|
|
case ISD::GlobalTLSAddress:
|
|
return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
|
|
case ISD::BlockAddress:
|
|
return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
|
|
case ISD::JumpTable:
|
|
return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
|
|
case ISD::ConstantPool:
|
|
return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
|
|
case ISD::BITCAST:
|
|
return lowerBITCAST(Op, DAG);
|
|
case ISD::VASTART:
|
|
return lowerVASTART(Op, DAG);
|
|
case ISD::VACOPY:
|
|
return lowerVACOPY(Op, DAG);
|
|
case ISD::DYNAMIC_STACKALLOC:
|
|
return lowerDYNAMIC_STACKALLOC(Op, DAG);
|
|
case ISD::UMUL_LOHI:
|
|
return lowerUMUL_LOHI(Op, DAG);
|
|
case ISD::SDIVREM:
|
|
return lowerSDIVREM(Op, DAG);
|
|
case ISD::UDIVREM:
|
|
return lowerUDIVREM(Op, DAG);
|
|
case ISD::OR:
|
|
return lowerOR(Op, DAG);
|
|
case ISD::ATOMIC_SWAP:
|
|
return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_SWAPW);
|
|
case ISD::ATOMIC_LOAD_ADD:
|
|
return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
|
|
case ISD::ATOMIC_LOAD_SUB:
|
|
return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
|
|
case ISD::ATOMIC_LOAD_AND:
|
|
return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
|
|
case ISD::ATOMIC_LOAD_OR:
|
|
return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
|
|
case ISD::ATOMIC_LOAD_XOR:
|
|
return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
|
|
case ISD::ATOMIC_LOAD_NAND:
|
|
return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
|
|
case ISD::ATOMIC_LOAD_MIN:
|
|
return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
|
|
case ISD::ATOMIC_LOAD_MAX:
|
|
return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
|
|
case ISD::ATOMIC_LOAD_UMIN:
|
|
return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
|
|
case ISD::ATOMIC_LOAD_UMAX:
|
|
return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
|
|
case ISD::ATOMIC_CMP_SWAP:
|
|
return lowerATOMIC_CMP_SWAP(Op, DAG);
|
|
case ISD::STACKSAVE:
|
|
return lowerSTACKSAVE(Op, DAG);
|
|
case ISD::STACKRESTORE:
|
|
return lowerSTACKRESTORE(Op, DAG);
|
|
default:
|
|
llvm_unreachable("Unexpected node to lower");
|
|
}
|
|
}
|
|
|
|
const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|
#define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
|
|
switch (Opcode) {
|
|
OPCODE(RET_FLAG);
|
|
OPCODE(CALL);
|
|
OPCODE(PCREL_WRAPPER);
|
|
OPCODE(CMP);
|
|
OPCODE(UCMP);
|
|
OPCODE(BR_CCMASK);
|
|
OPCODE(SELECT_CCMASK);
|
|
OPCODE(ADJDYNALLOC);
|
|
OPCODE(EXTRACT_ACCESS);
|
|
OPCODE(UMUL_LOHI64);
|
|
OPCODE(SDIVREM64);
|
|
OPCODE(UDIVREM32);
|
|
OPCODE(UDIVREM64);
|
|
OPCODE(ATOMIC_SWAPW);
|
|
OPCODE(ATOMIC_LOADW_ADD);
|
|
OPCODE(ATOMIC_LOADW_SUB);
|
|
OPCODE(ATOMIC_LOADW_AND);
|
|
OPCODE(ATOMIC_LOADW_OR);
|
|
OPCODE(ATOMIC_LOADW_XOR);
|
|
OPCODE(ATOMIC_LOADW_NAND);
|
|
OPCODE(ATOMIC_LOADW_MIN);
|
|
OPCODE(ATOMIC_LOADW_MAX);
|
|
OPCODE(ATOMIC_LOADW_UMIN);
|
|
OPCODE(ATOMIC_LOADW_UMAX);
|
|
OPCODE(ATOMIC_CMP_SWAPW);
|
|
}
|
|
return NULL;
|
|
#undef OPCODE
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Custom insertion
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Create a new basic block after MBB.
|
|
static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
|
|
MachineFunction &MF = *MBB->getParent();
|
|
MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
|
|
MF.insert(llvm::next(MachineFunction::iterator(MBB)), NewMBB);
|
|
return NewMBB;
|
|
}
|
|
|
|
// Split MBB after MI and return the new block (the one that contains
|
|
// instructions after MI).
|
|
static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
|
|
MachineBasicBlock *MBB) {
|
|
MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
|
|
NewMBB->splice(NewMBB->begin(), MBB,
|
|
llvm::next(MachineBasicBlock::iterator(MI)),
|
|
MBB->end());
|
|
NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
|
|
return NewMBB;
|
|
}
|
|
|
|
bool SystemZTargetLowering::
|
|
convertPrevCompareToBranch(MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
unsigned CCMask, MachineBasicBlock *Target) const {
|
|
MachineBasicBlock::iterator Compare = MBBI;
|
|
MachineBasicBlock::iterator Begin = MBB->begin();
|
|
do
|
|
{
|
|
if (Compare == Begin)
|
|
return false;
|
|
--Compare;
|
|
}
|
|
while (Compare->isDebugValue());
|
|
|
|
const SystemZInstrInfo *TII = TM.getInstrInfo();
|
|
unsigned FusedOpcode = TII->getCompareAndBranch(Compare->getOpcode(),
|
|
Compare);
|
|
if (!FusedOpcode)
|
|
return false;
|
|
|
|
DebugLoc DL = Compare->getDebugLoc();
|
|
BuildMI(*MBB, MBBI, DL, TII->get(FusedOpcode))
|
|
.addOperand(Compare->getOperand(0)).addOperand(Compare->getOperand(1))
|
|
.addImm(CCMask).addMBB(Target);
|
|
Compare->removeFromParent();
|
|
return true;
|
|
}
|
|
|
|
// Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
|
|
MachineBasicBlock *
|
|
SystemZTargetLowering::emitSelect(MachineInstr *MI,
|
|
MachineBasicBlock *MBB) const {
|
|
const SystemZInstrInfo *TII = TM.getInstrInfo();
|
|
|
|
unsigned DestReg = MI->getOperand(0).getReg();
|
|
unsigned TrueReg = MI->getOperand(1).getReg();
|
|
unsigned FalseReg = MI->getOperand(2).getReg();
|
|
unsigned CCMask = MI->getOperand(3).getImm();
|
|
DebugLoc DL = MI->getDebugLoc();
|
|
|
|
MachineBasicBlock *StartMBB = MBB;
|
|
MachineBasicBlock *JoinMBB = splitBlockAfter(MI, MBB);
|
|
MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
|
|
|
|
// StartMBB:
|
|
// BRC CCMask, JoinMBB
|
|
// # fallthrough to FalseMBB
|
|
//
|
|
// The original DAG glues comparisons to their uses, both to ensure
|
|
// that no CC-clobbering instructions are inserted between them, and
|
|
// to ensure that comparison results are not reused. This means that
|
|
// this Select is the sole user of any preceding comparison instruction
|
|
// and that we can try to use a fused compare and branch instead.
|
|
MBB = StartMBB;
|
|
if (!convertPrevCompareToBranch(MBB, MI, CCMask, JoinMBB))
|
|
BuildMI(MBB, DL, TII->get(SystemZ::BRC)).addImm(CCMask).addMBB(JoinMBB);
|
|
MBB->addSuccessor(JoinMBB);
|
|
MBB->addSuccessor(FalseMBB);
|
|
|
|
// FalseMBB:
|
|
// # fallthrough to JoinMBB
|
|
MBB = FalseMBB;
|
|
MBB->addSuccessor(JoinMBB);
|
|
|
|
// JoinMBB:
|
|
// %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
|
|
// ...
|
|
MBB = JoinMBB;
|
|
BuildMI(*MBB, MBB->begin(), DL, TII->get(SystemZ::PHI), DestReg)
|
|
.addReg(TrueReg).addMBB(StartMBB)
|
|
.addReg(FalseReg).addMBB(FalseMBB);
|
|
|
|
MI->eraseFromParent();
|
|
return JoinMBB;
|
|
}
|
|
|
|
// Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
|
|
// or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
|
|
// performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
|
|
// BitSize is the width of the field in bits, or 0 if this is a partword
|
|
// ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
|
|
// is one of the operands. Invert says whether the field should be
|
|
// inverted after performing BinOpcode (e.g. for NAND).
|
|
MachineBasicBlock *
|
|
SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
|
|
MachineBasicBlock *MBB,
|
|
unsigned BinOpcode,
|
|
unsigned BitSize,
|
|
bool Invert) const {
|
|
const SystemZInstrInfo *TII = TM.getInstrInfo();
|
|
MachineFunction &MF = *MBB->getParent();
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
unsigned MaskNE = CCMaskForCondCode(ISD::SETNE);
|
|
bool IsSubWord = (BitSize < 32);
|
|
|
|
// Extract the operands. Base can be a register or a frame index.
|
|
// Src2 can be a register or immediate.
|
|
unsigned Dest = MI->getOperand(0).getReg();
|
|
MachineOperand Base = earlyUseOperand(MI->getOperand(1));
|
|
int64_t Disp = MI->getOperand(2).getImm();
|
|
MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
|
|
unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
|
|
unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
|
|
DebugLoc DL = MI->getDebugLoc();
|
|
if (IsSubWord)
|
|
BitSize = MI->getOperand(6).getImm();
|
|
|
|
// Subword operations use 32-bit registers.
|
|
const TargetRegisterClass *RC = (BitSize <= 32 ?
|
|
&SystemZ::GR32BitRegClass :
|
|
&SystemZ::GR64BitRegClass);
|
|
unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
|
|
unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
|
|
|
|
// Get the right opcodes for the displacement.
|
|
LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
|
|
CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
|
|
assert(LOpcode && CSOpcode && "Displacement out of range");
|
|
|
|
// Create virtual registers for temporary results.
|
|
unsigned OrigVal = MRI.createVirtualRegister(RC);
|
|
unsigned OldVal = MRI.createVirtualRegister(RC);
|
|
unsigned NewVal = (BinOpcode || IsSubWord ?
|
|
MRI.createVirtualRegister(RC) : Src2.getReg());
|
|
unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
|
|
unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
|
|
|
|
// Insert a basic block for the main loop.
|
|
MachineBasicBlock *StartMBB = MBB;
|
|
MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
|
|
MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
|
|
|
|
// StartMBB:
|
|
// ...
|
|
// %OrigVal = L Disp(%Base)
|
|
// # fall through to LoopMMB
|
|
MBB = StartMBB;
|
|
BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
|
|
.addOperand(Base).addImm(Disp).addReg(0);
|
|
MBB->addSuccessor(LoopMBB);
|
|
|
|
// LoopMBB:
|
|
// %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
|
|
// %RotatedOldVal = RLL %OldVal, 0(%BitShift)
|
|
// %RotatedNewVal = OP %RotatedOldVal, %Src2
|
|
// %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
|
|
// %Dest = CS %OldVal, %NewVal, Disp(%Base)
|
|
// JNE LoopMBB
|
|
// # fall through to DoneMMB
|
|
MBB = LoopMBB;
|
|
BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
|
|
.addReg(OrigVal).addMBB(StartMBB)
|
|
.addReg(Dest).addMBB(LoopMBB);
|
|
if (IsSubWord)
|
|
BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
|
|
.addReg(OldVal).addReg(BitShift).addImm(0);
|
|
if (Invert) {
|
|
// Perform the operation normally and then invert every bit of the field.
|
|
unsigned Tmp = MRI.createVirtualRegister(RC);
|
|
BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
|
|
.addReg(RotatedOldVal).addOperand(Src2);
|
|
if (BitSize < 32)
|
|
// XILF with the upper BitSize bits set.
|
|
BuildMI(MBB, DL, TII->get(SystemZ::XILF32), RotatedNewVal)
|
|
.addReg(Tmp).addImm(uint32_t(~0 << (32 - BitSize)));
|
|
else if (BitSize == 32)
|
|
// XILF with every bit set.
|
|
BuildMI(MBB, DL, TII->get(SystemZ::XILF32), RotatedNewVal)
|
|
.addReg(Tmp).addImm(~uint32_t(0));
|
|
else {
|
|
// Use LCGR and add -1 to the result, which is more compact than
|
|
// an XILF, XILH pair.
|
|
unsigned Tmp2 = MRI.createVirtualRegister(RC);
|
|
BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
|
|
BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
|
|
.addReg(Tmp2).addImm(-1);
|
|
}
|
|
} else if (BinOpcode)
|
|
// A simply binary operation.
|
|
BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
|
|
.addReg(RotatedOldVal).addOperand(Src2);
|
|
else if (IsSubWord)
|
|
// Use RISBG to rotate Src2 into position and use it to replace the
|
|
// field in RotatedOldVal.
|
|
BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
|
|
.addReg(RotatedOldVal).addReg(Src2.getReg())
|
|
.addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
|
|
if (IsSubWord)
|
|
BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
|
|
.addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
|
|
BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
|
|
.addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
|
|
BuildMI(MBB, DL, TII->get(SystemZ::BRC)).addImm(MaskNE).addMBB(LoopMBB);
|
|
MBB->addSuccessor(LoopMBB);
|
|
MBB->addSuccessor(DoneMBB);
|
|
|
|
MI->eraseFromParent();
|
|
return DoneMBB;
|
|
}
|
|
|
|
// Implement EmitInstrWithCustomInserter for pseudo
|
|
// ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
|
|
// instruction that should be used to compare the current field with the
|
|
// minimum or maximum value. KeepOldMask is the BRC condition-code mask
|
|
// for when the current field should be kept. BitSize is the width of
|
|
// the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
|
|
MachineBasicBlock *
|
|
SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
|
|
MachineBasicBlock *MBB,
|
|
unsigned CompareOpcode,
|
|
unsigned KeepOldMask,
|
|
unsigned BitSize) const {
|
|
const SystemZInstrInfo *TII = TM.getInstrInfo();
|
|
MachineFunction &MF = *MBB->getParent();
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
unsigned MaskNE = CCMaskForCondCode(ISD::SETNE);
|
|
bool IsSubWord = (BitSize < 32);
|
|
|
|
// Extract the operands. Base can be a register or a frame index.
|
|
unsigned Dest = MI->getOperand(0).getReg();
|
|
MachineOperand Base = earlyUseOperand(MI->getOperand(1));
|
|
int64_t Disp = MI->getOperand(2).getImm();
|
|
unsigned Src2 = MI->getOperand(3).getReg();
|
|
unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
|
|
unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
|
|
DebugLoc DL = MI->getDebugLoc();
|
|
if (IsSubWord)
|
|
BitSize = MI->getOperand(6).getImm();
|
|
|
|
// Subword operations use 32-bit registers.
|
|
const TargetRegisterClass *RC = (BitSize <= 32 ?
|
|
&SystemZ::GR32BitRegClass :
|
|
&SystemZ::GR64BitRegClass);
|
|
unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
|
|
unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
|
|
|
|
// Get the right opcodes for the displacement.
|
|
LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
|
|
CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
|
|
assert(LOpcode && CSOpcode && "Displacement out of range");
|
|
|
|
// Create virtual registers for temporary results.
|
|
unsigned OrigVal = MRI.createVirtualRegister(RC);
|
|
unsigned OldVal = MRI.createVirtualRegister(RC);
|
|
unsigned NewVal = MRI.createVirtualRegister(RC);
|
|
unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
|
|
unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
|
|
unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
|
|
|
|
// Insert 3 basic blocks for the loop.
|
|
MachineBasicBlock *StartMBB = MBB;
|
|
MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
|
|
MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
|
|
MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
|
|
MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
|
|
|
|
// StartMBB:
|
|
// ...
|
|
// %OrigVal = L Disp(%Base)
|
|
// # fall through to LoopMMB
|
|
MBB = StartMBB;
|
|
BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
|
|
.addOperand(Base).addImm(Disp).addReg(0);
|
|
MBB->addSuccessor(LoopMBB);
|
|
|
|
// LoopMBB:
|
|
// %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
|
|
// %RotatedOldVal = RLL %OldVal, 0(%BitShift)
|
|
// CompareOpcode %RotatedOldVal, %Src2
|
|
// BRC KeepOldMask, UpdateMBB
|
|
MBB = LoopMBB;
|
|
BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
|
|
.addReg(OrigVal).addMBB(StartMBB)
|
|
.addReg(Dest).addMBB(UpdateMBB);
|
|
if (IsSubWord)
|
|
BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
|
|
.addReg(OldVal).addReg(BitShift).addImm(0);
|
|
unsigned FusedOpcode = TII->getCompareAndBranch(CompareOpcode);
|
|
if (FusedOpcode)
|
|
BuildMI(MBB, DL, TII->get(FusedOpcode))
|
|
.addReg(RotatedOldVal).addReg(Src2)
|
|
.addImm(KeepOldMask).addMBB(UpdateMBB);
|
|
else {
|
|
BuildMI(MBB, DL, TII->get(CompareOpcode))
|
|
.addReg(RotatedOldVal).addReg(Src2);
|
|
BuildMI(MBB, DL, TII->get(SystemZ::BRC))
|
|
.addImm(KeepOldMask).addMBB(UpdateMBB);
|
|
}
|
|
MBB->addSuccessor(UpdateMBB);
|
|
MBB->addSuccessor(UseAltMBB);
|
|
|
|
// UseAltMBB:
|
|
// %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
|
|
// # fall through to UpdateMMB
|
|
MBB = UseAltMBB;
|
|
if (IsSubWord)
|
|
BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
|
|
.addReg(RotatedOldVal).addReg(Src2)
|
|
.addImm(32).addImm(31 + BitSize).addImm(0);
|
|
MBB->addSuccessor(UpdateMBB);
|
|
|
|
// UpdateMBB:
|
|
// %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
|
|
// [ %RotatedAltVal, UseAltMBB ]
|
|
// %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
|
|
// %Dest = CS %OldVal, %NewVal, Disp(%Base)
|
|
// JNE LoopMBB
|
|
// # fall through to DoneMMB
|
|
MBB = UpdateMBB;
|
|
BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
|
|
.addReg(RotatedOldVal).addMBB(LoopMBB)
|
|
.addReg(RotatedAltVal).addMBB(UseAltMBB);
|
|
if (IsSubWord)
|
|
BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
|
|
.addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
|
|
BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
|
|
.addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
|
|
BuildMI(MBB, DL, TII->get(SystemZ::BRC)).addImm(MaskNE).addMBB(LoopMBB);
|
|
MBB->addSuccessor(LoopMBB);
|
|
MBB->addSuccessor(DoneMBB);
|
|
|
|
MI->eraseFromParent();
|
|
return DoneMBB;
|
|
}
|
|
|
|
// Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
|
|
// instruction MI.
|
|
MachineBasicBlock *
|
|
SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
|
|
MachineBasicBlock *MBB) const {
|
|
const SystemZInstrInfo *TII = TM.getInstrInfo();
|
|
MachineFunction &MF = *MBB->getParent();
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
unsigned MaskNE = CCMaskForCondCode(ISD::SETNE);
|
|
|
|
// Extract the operands. Base can be a register or a frame index.
|
|
unsigned Dest = MI->getOperand(0).getReg();
|
|
MachineOperand Base = earlyUseOperand(MI->getOperand(1));
|
|
int64_t Disp = MI->getOperand(2).getImm();
|
|
unsigned OrigCmpVal = MI->getOperand(3).getReg();
|
|
unsigned OrigSwapVal = MI->getOperand(4).getReg();
|
|
unsigned BitShift = MI->getOperand(5).getReg();
|
|
unsigned NegBitShift = MI->getOperand(6).getReg();
|
|
int64_t BitSize = MI->getOperand(7).getImm();
|
|
DebugLoc DL = MI->getDebugLoc();
|
|
|
|
const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
|
|
|
|
// Get the right opcodes for the displacement.
|
|
unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
|
|
unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
|
|
assert(LOpcode && CSOpcode && "Displacement out of range");
|
|
|
|
// Create virtual registers for temporary results.
|
|
unsigned OrigOldVal = MRI.createVirtualRegister(RC);
|
|
unsigned OldVal = MRI.createVirtualRegister(RC);
|
|
unsigned CmpVal = MRI.createVirtualRegister(RC);
|
|
unsigned SwapVal = MRI.createVirtualRegister(RC);
|
|
unsigned StoreVal = MRI.createVirtualRegister(RC);
|
|
unsigned RetryOldVal = MRI.createVirtualRegister(RC);
|
|
unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
|
|
unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
|
|
|
|
// Insert 2 basic blocks for the loop.
|
|
MachineBasicBlock *StartMBB = MBB;
|
|
MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
|
|
MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
|
|
MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
|
|
|
|
// StartMBB:
|
|
// ...
|
|
// %OrigOldVal = L Disp(%Base)
|
|
// # fall through to LoopMMB
|
|
MBB = StartMBB;
|
|
BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
|
|
.addOperand(Base).addImm(Disp).addReg(0);
|
|
MBB->addSuccessor(LoopMBB);
|
|
|
|
// LoopMBB:
|
|
// %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
|
|
// %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
|
|
// %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
|
|
// %Dest = RLL %OldVal, BitSize(%BitShift)
|
|
// ^^ The low BitSize bits contain the field
|
|
// of interest.
|
|
// %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
|
|
// ^^ Replace the upper 32-BitSize bits of the
|
|
// comparison value with those that we loaded,
|
|
// so that we can use a full word comparison.
|
|
// CRJNE %Dest, %RetryCmpVal, DoneMBB
|
|
// # Fall through to SetMBB
|
|
MBB = LoopMBB;
|
|
BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
|
|
.addReg(OrigOldVal).addMBB(StartMBB)
|
|
.addReg(RetryOldVal).addMBB(SetMBB);
|
|
BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
|
|
.addReg(OrigCmpVal).addMBB(StartMBB)
|
|
.addReg(RetryCmpVal).addMBB(SetMBB);
|
|
BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
|
|
.addReg(OrigSwapVal).addMBB(StartMBB)
|
|
.addReg(RetrySwapVal).addMBB(SetMBB);
|
|
BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
|
|
.addReg(OldVal).addReg(BitShift).addImm(BitSize);
|
|
BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
|
|
.addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
|
|
BuildMI(MBB, DL, TII->get(SystemZ::CRJ))
|
|
.addReg(Dest).addReg(RetryCmpVal)
|
|
.addImm(MaskNE).addMBB(DoneMBB);
|
|
MBB->addSuccessor(DoneMBB);
|
|
MBB->addSuccessor(SetMBB);
|
|
|
|
// SetMBB:
|
|
// %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
|
|
// ^^ Replace the upper 32-BitSize bits of the new
|
|
// value with those that we loaded.
|
|
// %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
|
|
// ^^ Rotate the new field to its proper position.
|
|
// %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
|
|
// JNE LoopMBB
|
|
// # fall through to ExitMMB
|
|
MBB = SetMBB;
|
|
BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
|
|
.addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
|
|
BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
|
|
.addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
|
|
BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
|
|
.addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
|
|
BuildMI(MBB, DL, TII->get(SystemZ::BRC)).addImm(MaskNE).addMBB(LoopMBB);
|
|
MBB->addSuccessor(LoopMBB);
|
|
MBB->addSuccessor(DoneMBB);
|
|
|
|
MI->eraseFromParent();
|
|
return DoneMBB;
|
|
}
|
|
|
|
// Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
|
|
// if the high register of the GR128 value must be cleared or false if
|
|
// it's "don't care". SubReg is subreg_odd32 when extending a GR32
|
|
// and subreg_odd when extending a GR64.
|
|
MachineBasicBlock *
|
|
SystemZTargetLowering::emitExt128(MachineInstr *MI,
|
|
MachineBasicBlock *MBB,
|
|
bool ClearEven, unsigned SubReg) const {
|
|
const SystemZInstrInfo *TII = TM.getInstrInfo();
|
|
MachineFunction &MF = *MBB->getParent();
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
DebugLoc DL = MI->getDebugLoc();
|
|
|
|
unsigned Dest = MI->getOperand(0).getReg();
|
|
unsigned Src = MI->getOperand(1).getReg();
|
|
unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
|
|
|
|
BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
|
|
if (ClearEven) {
|
|
unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
|
|
unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
|
|
|
|
BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
|
|
.addImm(0);
|
|
BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
|
|
.addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_high);
|
|
In128 = NewIn128;
|
|
}
|
|
BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
|
|
.addReg(In128).addReg(Src).addImm(SubReg);
|
|
|
|
MI->eraseFromParent();
|
|
return MBB;
|
|
}
|
|
|
|
MachineBasicBlock *SystemZTargetLowering::
|
|
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
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switch (MI->getOpcode()) {
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case SystemZ::Select32:
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case SystemZ::SelectF32:
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case SystemZ::Select64:
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case SystemZ::SelectF64:
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case SystemZ::SelectF128:
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return emitSelect(MI, MBB);
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case SystemZ::AEXT128_64:
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return emitExt128(MI, MBB, false, SystemZ::subreg_low);
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case SystemZ::ZEXT128_32:
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return emitExt128(MI, MBB, true, SystemZ::subreg_low32);
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case SystemZ::ZEXT128_64:
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return emitExt128(MI, MBB, true, SystemZ::subreg_low);
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case SystemZ::ATOMIC_SWAPW:
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return emitAtomicLoadBinary(MI, MBB, 0, 0);
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case SystemZ::ATOMIC_SWAP_32:
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return emitAtomicLoadBinary(MI, MBB, 0, 32);
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case SystemZ::ATOMIC_SWAP_64:
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return emitAtomicLoadBinary(MI, MBB, 0, 64);
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case SystemZ::ATOMIC_LOADW_AR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
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case SystemZ::ATOMIC_LOADW_AFI:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
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case SystemZ::ATOMIC_LOAD_AR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
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case SystemZ::ATOMIC_LOAD_AHI:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
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case SystemZ::ATOMIC_LOAD_AFI:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
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case SystemZ::ATOMIC_LOAD_AGR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
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case SystemZ::ATOMIC_LOAD_AGHI:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
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case SystemZ::ATOMIC_LOAD_AGFI:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
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case SystemZ::ATOMIC_LOADW_SR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
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case SystemZ::ATOMIC_LOAD_SR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
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case SystemZ::ATOMIC_LOAD_SGR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
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case SystemZ::ATOMIC_LOADW_NR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
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case SystemZ::ATOMIC_LOADW_NILH:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 0);
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case SystemZ::ATOMIC_LOAD_NR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
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case SystemZ::ATOMIC_LOAD_NILL32:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL32, 32);
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case SystemZ::ATOMIC_LOAD_NILH32:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 32);
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case SystemZ::ATOMIC_LOAD_NILF32:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF32, 32);
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case SystemZ::ATOMIC_LOAD_NGR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
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case SystemZ::ATOMIC_LOAD_NILL:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 64);
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case SystemZ::ATOMIC_LOAD_NILH:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 64);
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case SystemZ::ATOMIC_LOAD_NIHL:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64);
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case SystemZ::ATOMIC_LOAD_NIHH:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64);
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case SystemZ::ATOMIC_LOAD_NILF:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 64);
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case SystemZ::ATOMIC_LOAD_NIHF:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64);
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case SystemZ::ATOMIC_LOADW_OR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
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case SystemZ::ATOMIC_LOADW_OILH:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH32, 0);
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case SystemZ::ATOMIC_LOAD_OR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
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case SystemZ::ATOMIC_LOAD_OILL32:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL32, 32);
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case SystemZ::ATOMIC_LOAD_OILH32:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH32, 32);
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case SystemZ::ATOMIC_LOAD_OILF32:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF32, 32);
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case SystemZ::ATOMIC_LOAD_OGR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
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case SystemZ::ATOMIC_LOAD_OILL:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 64);
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case SystemZ::ATOMIC_LOAD_OILH:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 64);
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case SystemZ::ATOMIC_LOAD_OIHL:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL, 64);
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case SystemZ::ATOMIC_LOAD_OIHH:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH, 64);
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case SystemZ::ATOMIC_LOAD_OILF:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 64);
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case SystemZ::ATOMIC_LOAD_OIHF:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF, 64);
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case SystemZ::ATOMIC_LOADW_XR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
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case SystemZ::ATOMIC_LOADW_XILF:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF32, 0);
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case SystemZ::ATOMIC_LOAD_XR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
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case SystemZ::ATOMIC_LOAD_XILF32:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF32, 32);
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case SystemZ::ATOMIC_LOAD_XGR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
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case SystemZ::ATOMIC_LOAD_XILF:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 64);
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case SystemZ::ATOMIC_LOAD_XIHF:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF, 64);
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case SystemZ::ATOMIC_LOADW_NRi:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
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case SystemZ::ATOMIC_LOADW_NILHi:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 0, true);
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case SystemZ::ATOMIC_LOAD_NRi:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
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case SystemZ::ATOMIC_LOAD_NILL32i:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL32, 32, true);
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case SystemZ::ATOMIC_LOAD_NILH32i:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 32, true);
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case SystemZ::ATOMIC_LOAD_NILF32i:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF32, 32, true);
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case SystemZ::ATOMIC_LOAD_NGRi:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
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case SystemZ::ATOMIC_LOAD_NILLi:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 64, true);
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case SystemZ::ATOMIC_LOAD_NILHi:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 64, true);
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case SystemZ::ATOMIC_LOAD_NIHLi:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64, true);
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case SystemZ::ATOMIC_LOAD_NIHHi:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64, true);
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case SystemZ::ATOMIC_LOAD_NILFi:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 64, true);
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case SystemZ::ATOMIC_LOAD_NIHFi:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64, true);
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case SystemZ::ATOMIC_LOADW_MIN:
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return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
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SystemZ::CCMASK_CMP_LE, 0);
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case SystemZ::ATOMIC_LOAD_MIN_32:
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return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
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SystemZ::CCMASK_CMP_LE, 32);
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case SystemZ::ATOMIC_LOAD_MIN_64:
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return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
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SystemZ::CCMASK_CMP_LE, 64);
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case SystemZ::ATOMIC_LOADW_MAX:
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return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
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SystemZ::CCMASK_CMP_GE, 0);
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case SystemZ::ATOMIC_LOAD_MAX_32:
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return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
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SystemZ::CCMASK_CMP_GE, 32);
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case SystemZ::ATOMIC_LOAD_MAX_64:
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return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
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SystemZ::CCMASK_CMP_GE, 64);
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case SystemZ::ATOMIC_LOADW_UMIN:
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return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
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SystemZ::CCMASK_CMP_LE, 0);
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case SystemZ::ATOMIC_LOAD_UMIN_32:
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return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
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SystemZ::CCMASK_CMP_LE, 32);
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case SystemZ::ATOMIC_LOAD_UMIN_64:
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return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
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SystemZ::CCMASK_CMP_LE, 64);
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case SystemZ::ATOMIC_LOADW_UMAX:
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return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
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SystemZ::CCMASK_CMP_GE, 0);
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case SystemZ::ATOMIC_LOAD_UMAX_32:
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return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
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SystemZ::CCMASK_CMP_GE, 32);
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case SystemZ::ATOMIC_LOAD_UMAX_64:
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return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
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SystemZ::CCMASK_CMP_GE, 64);
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case SystemZ::ATOMIC_CMP_SWAPW:
|
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return emitAtomicCmpSwapW(MI, MBB);
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case SystemZ::BRC:
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// The original DAG glues comparisons to their uses, both to ensure
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// that no CC-clobbering instructions are inserted between them, and
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|
// to ensure that comparison results are not reused. This means that
|
|
// a BRC is the sole user of a preceding comparison and that we can
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// try to use a fused compare and branch instead.
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if (convertPrevCompareToBranch(MBB, MI, MI->getOperand(0).getImm(),
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MI->getOperand(1).getMBB()))
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MI->eraseFromParent();
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return MBB;
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default:
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llvm_unreachable("Unexpected instr type to insert");
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|
}
|
|
}
|