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https://github.com/c64scene-ar/llvm-6502.git
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7d24705f65
callee-saved registers at the end of the lists. Also prefer to avoid using the low registers that are in register subclasses required by certain instructions, so that those registers will more likely be available when needed. This change makes a huge improvement in spilling in some cases. Thanks to Jakob for helping me realize the problem. Most of this patch is fixing the testsuite. There are quite a few places where we're checking for specific registers. I changed those to wildcards in places where that doesn't weaken the tests. The spill-q.ll and thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch of live values to force spills on those tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
213 lines
6.3 KiB
LLVM
213 lines
6.3 KiB
LLVM
; RUN: llc < %s -mattr=+neon | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
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target triple = "thumbv7-elf"
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define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
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;CHECK: vget_lanes8:
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;CHECK: vmov.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = extractelement <8 x i8> %tmp1, i32 1
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%tmp3 = sext i8 %tmp2 to i32
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ret i32 %tmp3
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}
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define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
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;CHECK: vget_lanes16:
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;CHECK: vmov.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = extractelement <4 x i16> %tmp1, i32 1
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%tmp3 = sext i16 %tmp2 to i32
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ret i32 %tmp3
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}
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define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
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;CHECK: vget_laneu8:
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;CHECK: vmov.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = extractelement <8 x i8> %tmp1, i32 1
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%tmp3 = zext i8 %tmp2 to i32
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ret i32 %tmp3
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}
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define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
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;CHECK: vget_laneu16:
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;CHECK: vmov.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = extractelement <4 x i16> %tmp1, i32 1
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%tmp3 = zext i16 %tmp2 to i32
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ret i32 %tmp3
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}
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; Do a vector add to keep the extraction from being done directly from memory.
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define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
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;CHECK: vget_lanei32:
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;CHECK: vmov.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = add <2 x i32> %tmp1, %tmp1
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%tmp3 = extractelement <2 x i32> %tmp2, i32 1
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ret i32 %tmp3
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}
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define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
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;CHECK: vgetQ_lanes8:
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;CHECK: vmov.s8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = extractelement <16 x i8> %tmp1, i32 1
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%tmp3 = sext i8 %tmp2 to i32
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ret i32 %tmp3
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}
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define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
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;CHECK: vgetQ_lanes16:
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;CHECK: vmov.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = extractelement <8 x i16> %tmp1, i32 1
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%tmp3 = sext i16 %tmp2 to i32
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ret i32 %tmp3
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}
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define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
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;CHECK: vgetQ_laneu8:
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;CHECK: vmov.u8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = extractelement <16 x i8> %tmp1, i32 1
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%tmp3 = zext i8 %tmp2 to i32
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ret i32 %tmp3
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}
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define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
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;CHECK: vgetQ_laneu16:
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;CHECK: vmov.u16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = extractelement <8 x i16> %tmp1, i32 1
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%tmp3 = zext i16 %tmp2 to i32
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ret i32 %tmp3
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}
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; Do a vector add to keep the extraction from being done directly from memory.
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define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind {
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;CHECK: vgetQ_lanei32:
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;CHECK: vmov.32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = add <4 x i32> %tmp1, %tmp1
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%tmp3 = extractelement <4 x i32> %tmp2, i32 1
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ret i32 %tmp3
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}
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define arm_aapcs_vfpcc void @test_vget_laneu16() nounwind {
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entry:
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; CHECK: vmov.u16 r0, d{{.*}}[1]
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%arg0_uint16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1]
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%out_uint16_t = alloca i16 ; <i16*> [#uses=1]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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%0 = load <4 x i16>* %arg0_uint16x4_t, align 8 ; <<4 x i16>> [#uses=1]
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%1 = extractelement <4 x i16> %0, i32 1 ; <i16> [#uses=1]
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store i16 %1, i16* %out_uint16_t, align 2
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br label %return
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return: ; preds = %entry
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ret void
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}
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define arm_aapcs_vfpcc void @test_vget_laneu8() nounwind {
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entry:
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; CHECK: vmov.u8 r0, d{{.*}}[1]
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%arg0_uint8x8_t = alloca <8 x i8> ; <<8 x i8>*> [#uses=1]
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%out_uint8_t = alloca i8 ; <i8*> [#uses=1]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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%0 = load <8 x i8>* %arg0_uint8x8_t, align 8 ; <<8 x i8>> [#uses=1]
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%1 = extractelement <8 x i8> %0, i32 1 ; <i8> [#uses=1]
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store i8 %1, i8* %out_uint8_t, align 1
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br label %return
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return: ; preds = %entry
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ret void
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}
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define arm_aapcs_vfpcc void @test_vgetQ_laneu16() nounwind {
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entry:
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; CHECK: vmov.u16 r0, d{{.*}}[1]
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%arg0_uint16x8_t = alloca <8 x i16> ; <<8 x i16>*> [#uses=1]
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%out_uint16_t = alloca i16 ; <i16*> [#uses=1]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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%0 = load <8 x i16>* %arg0_uint16x8_t, align 16 ; <<8 x i16>> [#uses=1]
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%1 = extractelement <8 x i16> %0, i32 1 ; <i16> [#uses=1]
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store i16 %1, i16* %out_uint16_t, align 2
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br label %return
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return: ; preds = %entry
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ret void
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}
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define arm_aapcs_vfpcc void @test_vgetQ_laneu8() nounwind {
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entry:
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; CHECK: vmov.u8 r0, d{{.*}}[1]
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%arg0_uint8x16_t = alloca <16 x i8> ; <<16 x i8>*> [#uses=1]
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%out_uint8_t = alloca i8 ; <i8*> [#uses=1]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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%0 = load <16 x i8>* %arg0_uint8x16_t, align 16 ; <<16 x i8>> [#uses=1]
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%1 = extractelement <16 x i8> %0, i32 1 ; <i8> [#uses=1]
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store i8 %1, i8* %out_uint8_t, align 1
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br label %return
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return: ; preds = %entry
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ret void
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}
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define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
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;CHECK: vset_lane8:
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;CHECK: vmov.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
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;CHECK: vset_lane16:
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;CHECK: vmov.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
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;CHECK: vset_lane32:
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;CHECK: vmov.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1
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ret <2 x i32> %tmp2
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}
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define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
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;CHECK: vsetQ_lane8:
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;CHECK: vmov.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
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;CHECK: vsetQ_lane16:
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;CHECK: vmov.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
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;CHECK: vsetQ_lane32:
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;CHECK: vmov.32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1
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ret <4 x i32> %tmp2
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}
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define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind {
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;CHECK: test_vset_lanef32:
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;CHECK: vmov.f32 s3, s0
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;CHECK: vmov.f64 d0, d1
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entry:
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%0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1]
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ret <2 x float> %0
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}
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