mirror of
https://github.com/c64scene-ar/llvm-6502.git
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82203218d1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117469 91177308-0d34-0410-b5e6-96231b3b80d8
307 lines
10 KiB
LLVM
307 lines
10 KiB
LLVM
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
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; CHECK: vmov_8xi8
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define <8 x i8> @vmov_8xi8() nounwind {
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; CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2]
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ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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; CHECK: vmov_4xi16a
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define <4 x i16> @vmov_4xi16a() nounwind {
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; CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2]
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ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
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}
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; CHECK: vmov_4xi16b
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define <4 x i16> @vmov_4xi16b() nounwind {
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; CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2]
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ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
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}
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; CHECK: vmov_2xi32a
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define <2 x i32> @vmov_2xi32a() nounwind {
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; CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2]
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ret <2 x i32> < i32 32, i32 32 >
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}
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; CHECK: vmov_2xi32b
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define <2 x i32> @vmov_2xi32b() nounwind {
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; CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2]
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ret <2 x i32> < i32 8192, i32 8192 >
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}
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; CHECK: vmov_2xi32c
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define <2 x i32> @vmov_2xi32c() nounwind {
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; CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2]
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ret <2 x i32> < i32 2097152, i32 2097152 >
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}
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; CHECK: vmov_2xi32d
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define <2 x i32> @vmov_2xi32d() nounwind {
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; CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2]
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ret <2 x i32> < i32 536870912, i32 536870912 >
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}
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; CHECK: vmov_2xi32e
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define <2 x i32> @vmov_2xi32e() nounwind {
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; CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2]
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ret <2 x i32> < i32 8447, i32 8447 >
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}
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; CHECK: vmov_2xi32f
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define <2 x i32> @vmov_2xi32f() nounwind {
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; CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2]
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ret <2 x i32> < i32 2162687, i32 2162687 >
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}
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; CHECK: vmov_1xi64
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define <1 x i64> @vmov_1xi64() nounwind {
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; CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3]
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ret <1 x i64> < i64 18374687574888349695 >
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}
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; CHECK: vmov_16xi8
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define <16 x i8> @vmov_16xi8() nounwind {
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; CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2]
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ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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; CHECK: vmov_8xi16a
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define <8 x i16> @vmov_8xi16a() nounwind {
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; CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2]
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ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
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}
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; CHECK: vmov_8xi16b
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define <8 x i16> @vmov_8xi16b() nounwind {
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; CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2]
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ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
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}
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; CHECK: vmov_4xi32a
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define <4 x i32> @vmov_4xi32a() nounwind {
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; CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2]
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ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
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}
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; CHECK: vmov_4xi32b
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define <4 x i32> @vmov_4xi32b() nounwind {
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; CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2]
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ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
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}
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; CHECK: vmov_4xi32c
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define <4 x i32> @vmov_4xi32c() nounwind {
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; CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2]
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ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
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}
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; CHECK: vmov_4xi32d
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define <4 x i32> @vmov_4xi32d() nounwind {
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; CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2]
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ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
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}
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; CHECK: vmov_4xi32e
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define <4 x i32> @vmov_4xi32e() nounwind {
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; CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2]
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ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
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}
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; CHECK: vmov_4xi32f
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define <4 x i32> @vmov_4xi32f() nounwind {
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; CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2]
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ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
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}
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; CHECK: vmov_2xi64
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define <2 x i64> @vmov_2xi64() nounwind {
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; CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3]
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ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
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}
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; CHECK: vmvn_4xi16a
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define <4 x i16> @vmvn_4xi16a() nounwind {
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; CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2]
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ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
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}
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; CHECK: vmvn_4xi16b
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define <4 x i16> @vmvn_4xi16b() nounwind {
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; CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2]
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ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
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}
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; CHECK: vmvn_2xi32a
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define <2 x i32> @vmvn_2xi32a() nounwind {
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; CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2]
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ret <2 x i32> < i32 4294967263, i32 4294967263 >
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}
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; CHECK: vmvn_2xi32b
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define <2 x i32> @vmvn_2xi32b() nounwind {
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; CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2]
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ret <2 x i32> < i32 4294959103, i32 4294959103 >
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}
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; CHECK: vmvn_2xi32c
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define <2 x i32> @vmvn_2xi32c() nounwind {
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; CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2]
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ret <2 x i32> < i32 4292870143, i32 4292870143 >
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}
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; CHECK: vmvn_2xi32d
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define <2 x i32> @vmvn_2xi32d() nounwind {
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; CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2]
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ret <2 x i32> < i32 3758096383, i32 3758096383 >
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}
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; CHECK: vmvn_2xi32e
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define <2 x i32> @vmvn_2xi32e() nounwind {
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; CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2]
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ret <2 x i32> < i32 4294958848, i32 4294958848 >
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}
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; CHECK: vmvn_2xi32f
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define <2 x i32> @vmvn_2xi32f() nounwind {
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; CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2]
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ret <2 x i32> < i32 4292804608, i32 4292804608 >
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}
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define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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; CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf2]
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%tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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; CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf2]
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%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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; CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf2]
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%tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
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ret <2 x i64> %tmp2
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}
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define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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; CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf3]
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%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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; CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf3]
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%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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; CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf3]
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%tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
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ret <2 x i64> %tmp2
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}
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define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
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%tmp1 = load <8 x i16>* %A
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; CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xf3]
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%tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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; CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xf3]
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%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
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%tmp1 = load <2 x i64>* %A
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; CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xf3]
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%tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
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%tmp1 = load <8 x i16>* %A
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; CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xf3]
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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; CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xf3]
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
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%tmp1 = load <2 x i64>* %A
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; CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xf3]
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
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%tmp1 = load <8 x i16>* %A
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; CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xf3]
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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; CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xf3]
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
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%tmp1 = load <2 x i64>* %A
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; CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xf3]
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
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%tmp1 = load <8 x i16>* %A
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; CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xf3]
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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; CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xf3]
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
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%tmp1 = load <2 x i64>* %A
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; CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xf3]
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
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ret <2 x i32> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone |