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https://github.com/c64scene-ar/llvm-6502.git
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bcd2498f4f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32321 91177308-0d34-0410-b5e6-96231b3b80d8
468 lines
17 KiB
C++
468 lines
17 KiB
C++
//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveVariable analysis pass. For each machine
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// instruction in the function, this pass calculates the set of registers that
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// are immediately dead after the instruction (i.e., the instruction calculates
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// the value, but it is never used) and the set of registers that are used by
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// the instruction, but are never used after the instruction (i.e., they are
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// killed).
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//
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// This class computes live variables using are sparse implementation based on
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// the machine code SSA form. This class computes live variable information for
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// each virtual and _register allocatable_ physical register in a function. It
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// uses the dominance properties of SSA form to efficiently compute live
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// variables for virtual registers, and assumes that physical registers are only
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// live within a single basic block (allowing it to do a single local analysis
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// to resolve physical register lifetimes in each basic block). If a physical
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// register is not register allocatable, it is not tracked. This is useful for
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// things like the stack pointer and condition codes.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Config/alloca.h"
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#include <algorithm>
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using namespace llvm;
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static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
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void LiveVariables::VarInfo::dump() const {
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cerr << "Register Defined by: ";
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if (DefInst)
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cerr << *DefInst;
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else
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cerr << "<null>\n";
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cerr << " Alive in blocks: ";
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for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
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if (AliveBlocks[i]) cerr << i << ", ";
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cerr << "\n Killed by:";
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if (Kills.empty())
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cerr << " No instructions.\n";
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else {
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for (unsigned i = 0, e = Kills.size(); i != e; ++i)
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cerr << "\n #" << i << ": " << *Kills[i];
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cerr << "\n";
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}
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}
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LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
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assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
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"getVarInfo: not a virtual register!");
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RegIdx -= MRegisterInfo::FirstVirtualRegister;
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if (RegIdx >= VirtRegInfo.size()) {
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if (RegIdx >= 2*VirtRegInfo.size())
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VirtRegInfo.resize(RegIdx*2);
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else
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VirtRegInfo.resize(2*VirtRegInfo.size());
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}
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return VirtRegInfo[RegIdx];
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}
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/// registerOverlap - Returns true if register 1 is equal to register 2
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/// or if register 1 is equal to any of alias of register 2.
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static bool registerOverlap(unsigned Reg1, unsigned Reg2,
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const MRegisterInfo *RegInfo) {
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bool isVirt1 = MRegisterInfo::isVirtualRegister(Reg1);
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bool isVirt2 = MRegisterInfo::isVirtualRegister(Reg2);
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if (isVirt1 != isVirt2)
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return false;
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if (Reg1 == Reg2)
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return true;
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else if (isVirt1)
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return false;
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for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg2);
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unsigned Alias = *AliasSet; ++AliasSet) {
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if (Reg1 == Alias)
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return true;
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}
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return false;
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}
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bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isKill()) {
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if (registerOverlap(Reg, MO.getReg(), RegInfo))
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return true;
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}
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}
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return false;
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}
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bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDead())
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if (registerOverlap(Reg, MO.getReg(), RegInfo))
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return true;
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}
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return false;
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}
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bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDef()) {
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if (registerOverlap(Reg, MO.getReg(), RegInfo))
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return true;
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}
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}
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return false;
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}
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
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MachineBasicBlock *MBB) {
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unsigned BBNum = MBB->getNumber();
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// Check to see if this basic block is one of the killing blocks. If so,
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// remove it...
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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if (VRInfo.Kills[i]->getParent() == MBB) {
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VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
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break;
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}
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if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion
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if (VRInfo.AliveBlocks.size() <= BBNum)
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VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
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if (VRInfo.AliveBlocks[BBNum])
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return; // We already know the block is live
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// Mark the variable known alive in this bb
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VRInfo.AliveBlocks[BBNum] = true;
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for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
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E = MBB->pred_end(); PI != E; ++PI)
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MarkVirtRegAliveInBlock(VRInfo, *PI);
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}
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void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
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MachineInstr *MI) {
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assert(VRInfo.DefInst && "Register use before def!");
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// Check to see if this basic block is already a kill block...
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if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
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// Yes, this register is killed in this basic block already. Increase the
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// live range by updating the kill instruction.
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VRInfo.Kills.back() = MI;
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return;
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}
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#ifndef NDEBUG
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
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#endif
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assert(MBB != VRInfo.DefInst->getParent() &&
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"Should have kill for defblock!");
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// Add a new kill entry for this basic block.
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VRInfo.Kills.push_back(MI);
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// Update all dominating blocks to mark them known live.
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for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
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E = MBB->pred_end(); PI != E; ++PI)
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MarkVirtRegAliveInBlock(VRInfo, *PI);
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}
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void LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isUse() && MO.getReg() == IncomingReg) {
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MO.setIsKill();
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break;
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}
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}
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}
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void LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDef() && MO.getReg() == IncomingReg) {
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MO.setIsDead();
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break;
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}
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}
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}
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void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
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PhysRegInfo[Reg] = MI;
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PhysRegUsed[Reg] = true;
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for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
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unsigned Alias = *AliasSet; ++AliasSet) {
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PhysRegInfo[Alias] = MI;
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PhysRegUsed[Alias] = true;
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}
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}
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void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
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// Does this kill a previous version of this register?
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if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
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if (PhysRegUsed[Reg])
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addRegisterKilled(Reg, LastUse);
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else
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addRegisterDead(Reg, LastUse);
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}
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PhysRegInfo[Reg] = MI;
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PhysRegUsed[Reg] = false;
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for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
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unsigned Alias = *AliasSet; ++AliasSet) {
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if (MachineInstr *LastUse = PhysRegInfo[Alias]) {
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if (PhysRegUsed[Alias])
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addRegisterKilled(Alias, LastUse);
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else
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addRegisterDead(Alias, LastUse);
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}
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PhysRegInfo[Alias] = MI;
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PhysRegUsed[Alias] = false;
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}
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}
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bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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RegInfo = MF.getTarget().getRegisterInfo();
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assert(RegInfo && "Target doesn't have register information?");
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AllocatablePhysicalRegisters = RegInfo->getAllocatableSet(MF);
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// PhysRegInfo - Keep track of which instruction was the last use of a
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// physical register. This is a purely local property, because all physical
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// register references as presumed dead across basic blocks.
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//
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PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) *
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RegInfo->getNumRegs());
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PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs());
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std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0);
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/// Get some space for a respectable number of registers...
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VirtRegInfo.resize(64);
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// Mark live-in registers as live-in.
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for (MachineFunction::livein_iterator I = MF.livein_begin(),
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E = MF.livein_end(); I != E; ++I) {
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assert(MRegisterInfo::isPhysicalRegister(I->first) &&
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"Cannot have a live-in virtual register!");
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HandlePhysRegDef(I->first, 0);
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}
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analyzePHINodes(MF);
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// Calculate live variable information in depth first order on the CFG of the
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// function. This guarantees that we will see the definition of a virtual
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// register before its uses due to dominance properties of SSA (except for PHI
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// nodes, which are treated as a special case).
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//
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MachineBasicBlock *Entry = MF.begin();
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std::set<MachineBasicBlock*> Visited;
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for (df_ext_iterator<MachineBasicBlock*> DFI = df_ext_begin(Entry, Visited),
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E = df_ext_end(Entry, Visited); DFI != E; ++DFI) {
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MachineBasicBlock *MBB = *DFI;
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// Loop over all of the instructions, processing them.
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I) {
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MachineInstr *MI = I;
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// Process all of the operands of the instruction...
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unsigned NumOperandsToProcess = MI->getNumOperands();
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// Unless it is a PHI node. In this case, ONLY process the DEF, not any
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// of the uses. They will be handled in other basic blocks.
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if (MI->getOpcode() == TargetInstrInfo::PHI)
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NumOperandsToProcess = 1;
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// Process all uses...
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for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isUse() && MO.getReg()) {
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if (MRegisterInfo::isVirtualRegister(MO.getReg())){
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HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
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} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
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AllocatablePhysicalRegisters[MO.getReg()]) {
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HandlePhysRegUse(MO.getReg(), MI);
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}
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}
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}
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// Process all defs...
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for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isDef() && MO.getReg()) {
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if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
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VarInfo &VRInfo = getVarInfo(MO.getReg());
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assert(VRInfo.DefInst == 0 && "Variable multiply defined!");
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VRInfo.DefInst = MI;
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// Defaults to dead
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VRInfo.Kills.push_back(MI);
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} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
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AllocatablePhysicalRegisters[MO.getReg()]) {
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HandlePhysRegDef(MO.getReg(), MI);
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}
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}
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}
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}
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// Handle any virtual assignments from PHI nodes which might be at the
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// bottom of this basic block. We check all of our successor blocks to see
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// if they have PHI nodes, and if so, we simulate an assignment at the end
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// of the current block.
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if (!PHIVarInfo[MBB].empty()) {
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std::vector<unsigned>& VarInfoVec = PHIVarInfo[MBB];
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for (std::vector<unsigned>::iterator I = VarInfoVec.begin(),
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E = VarInfoVec.end(); I != E; ++I) {
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VarInfo& VRInfo = getVarInfo(*I);
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assert(VRInfo.DefInst && "Register use before def (or no def)!");
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// Only mark it alive only in the block we are representing.
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MarkVirtRegAliveInBlock(VRInfo, MBB);
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}
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}
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// Finally, if the last instruction in the block is a return, make sure to mark
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// it as using all of the live-out values in the function.
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if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
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MachineInstr *Ret = &MBB->back();
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for (MachineFunction::liveout_iterator I = MF.liveout_begin(),
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E = MF.liveout_end(); I != E; ++I) {
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assert(MRegisterInfo::isPhysicalRegister(*I) &&
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"Cannot have a live-in virtual register!");
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HandlePhysRegUse(*I, Ret);
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// Add live-out registers as implicit uses.
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Ret->addRegOperand(*I, false, true);
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}
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}
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// Loop over PhysRegInfo, killing any registers that are available at the
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// end of the basic block. This also resets the PhysRegInfo map.
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for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
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if (PhysRegInfo[i])
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HandlePhysRegDef(i, 0);
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}
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// Convert and transfer the dead / killed information we have gathered into
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// VirtRegInfo onto MI's.
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//
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for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
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for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
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if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst)
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addRegisterDead(i + MRegisterInfo::FirstVirtualRegister,
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VirtRegInfo[i].Kills[j]);
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else
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addRegisterKilled(i + MRegisterInfo::FirstVirtualRegister,
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VirtRegInfo[i].Kills[j]);
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}
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// Check to make sure there are no unreachable blocks in the MC CFG for the
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// function. If so, it is due to a bug in the instruction selector or some
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// other part of the code generator if this happens.
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#ifndef NDEBUG
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for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i)
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assert(Visited.count(&*i) != 0 && "unreachable basic block found");
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#endif
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PHIVarInfo.clear();
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return false;
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}
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/// instructionChanged - When the address of an instruction changes, this
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/// method should be called so that live variables can update its internal
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/// data structures. This removes the records for OldMI, transfering them to
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/// the records for NewMI.
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void LiveVariables::instructionChanged(MachineInstr *OldMI,
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MachineInstr *NewMI) {
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// If the instruction defines any virtual registers, update the VarInfo,
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// kill and dead information for the instruction.
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for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = OldMI->getOperand(i);
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if (MO.isRegister() && MO.getReg() &&
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MRegisterInfo::isVirtualRegister(MO.getReg())) {
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unsigned Reg = MO.getReg();
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VarInfo &VI = getVarInfo(Reg);
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if (MO.isDef()) {
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if (MO.isDead()) {
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MO.unsetIsDead();
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addVirtualRegisterDead(Reg, NewMI);
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}
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// Update the defining instruction.
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if (VI.DefInst == OldMI)
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VI.DefInst = NewMI;
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}
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if (MO.isUse()) {
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if (MO.isKill()) {
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MO.unsetIsKill();
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addVirtualRegisterKilled(Reg, NewMI);
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}
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// If this is a kill of the value, update the VI kills list.
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if (VI.removeKill(OldMI))
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VI.Kills.push_back(NewMI); // Yes, there was a kill of it
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}
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}
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}
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}
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/// removeVirtualRegistersKilled - Remove all killed info for the specified
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/// instruction.
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void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isKill()) {
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MO.unsetIsKill();
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unsigned Reg = MO.getReg();
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if (MRegisterInfo::isVirtualRegister(Reg)) {
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bool removed = getVarInfo(Reg).removeKill(MI);
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assert(removed && "kill not in register's VarInfo?");
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}
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}
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}
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}
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/// removeVirtualRegistersDead - Remove all of the dead registers for the
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/// specified instruction from the live variable information.
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void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDead()) {
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MO.unsetIsDead();
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unsigned Reg = MO.getReg();
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if (MRegisterInfo::isVirtualRegister(Reg)) {
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bool removed = getVarInfo(Reg).removeKill(MI);
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assert(removed && "kill not in register's VarInfo?");
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}
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}
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}
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}
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/// analyzePHINodes - Gather information about the PHI nodes in here. In
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/// particular, we want to map the variable information of a virtual
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/// register which is used in a PHI node. We map that to the BB the vreg is
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/// coming from.
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///
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void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
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for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
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I != E; ++I)
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for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
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BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
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for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
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PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()].
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push_back(BBI->getOperand(i).getReg());
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}
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