llvm-6502/test/CodeGen/R600/load-i1.ll
Tom Stellard 40e455d992 R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
SI_IF and SI_ELSE are terminators which also produce a value.  For
these instructions ISel always inserts a COPY to move their value
to another basic block.  This COPY ends up between SI_(IF|ELSE)
and the S_BRANCH* instruction at the end of the block.

This breaks MachineBasicBlock::getFirstTerminator() and also the
machine verifier which assumes that terminators are grouped together at
the end of blocks.

To solve this we coalesce the copy away right after ISel to make sure
there are no instructions in between terminators at the end of blocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207591 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:12:53 +00:00

108 lines
2.9 KiB
LLVM

; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
; SI-LABEL: @global_copy_i1_to_i1
; SI: BUFFER_LOAD_UBYTE
; SI: V_AND_B32_e32 v{{[0-9]+}}, 1
; SI: BUFFER_STORE_BYTE
; SI: S_ENDPGM
define void @global_copy_i1_to_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
%load = load i1 addrspace(1)* %in
store i1 %load, i1 addrspace(1)* %out, align 1
ret void
}
; SI-LABEL: @global_sextload_i1_to_i32
; XSI: BUFFER_LOAD_BYTE
; SI: BUFFER_STORE_DWORD
; SI: S_ENDPGM
define void @global_sextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
%load = load i1 addrspace(1)* %in
%ext = sext i1 %load to i32
store i32 %ext, i32 addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: @global_zextload_i1_to_i32
; SI: BUFFER_LOAD_UBYTE
; SI: BUFFER_STORE_DWORD
; SI: S_ENDPGM
define void @global_zextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
%load = load i1 addrspace(1)* %in
%ext = zext i1 %load to i32
store i32 %ext, i32 addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: @global_sextload_i1_to_i64
; XSI: BUFFER_LOAD_BYTE
; SI: BUFFER_STORE_DWORDX2
; SI: S_ENDPGM
define void @global_sextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
%load = load i1 addrspace(1)* %in
%ext = sext i1 %load to i64
store i64 %ext, i64 addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: @global_zextload_i1_to_i64
; SI: BUFFER_LOAD_UBYTE
; SI: BUFFER_STORE_DWORDX2
; SI: S_ENDPGM
define void @global_zextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
%load = load i1 addrspace(1)* %in
%ext = zext i1 %load to i64
store i64 %ext, i64 addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: @i1_arg
; SI: BUFFER_LOAD_UBYTE
; SI: V_AND_B32_e32
; SI: BUFFER_STORE_BYTE
; SI: S_ENDPGM
define void @i1_arg(i1 addrspace(1)* %out, i1 %x) nounwind {
store i1 %x, i1 addrspace(1)* %out, align 1
ret void
}
; SI-LABEL: @i1_arg_zext_i32
; SI: BUFFER_LOAD_UBYTE
; SI: BUFFER_STORE_DWORD
; SI: S_ENDPGM
define void @i1_arg_zext_i32(i32 addrspace(1)* %out, i1 %x) nounwind {
%ext = zext i1 %x to i32
store i32 %ext, i32 addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: @i1_arg_zext_i64
; SI: BUFFER_LOAD_UBYTE
; SI: BUFFER_STORE_DWORDX2
; SI: S_ENDPGM
define void @i1_arg_zext_i64(i64 addrspace(1)* %out, i1 %x) nounwind {
%ext = zext i1 %x to i64
store i64 %ext, i64 addrspace(1)* %out, align 8
ret void
}
; SI-LABEL: @i1_arg_sext_i32
; XSI: BUFFER_LOAD_BYTE
; SI: BUFFER_STORE_DWORD
; SI: S_ENDPGM
define void @i1_arg_sext_i32(i32 addrspace(1)* %out, i1 %x) nounwind {
%ext = sext i1 %x to i32
store i32 %ext, i32addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: @i1_arg_sext_i64
; XSI: BUFFER_LOAD_BYTE
; SI: BUFFER_STORE_DWORDX2
; SI: S_ENDPGM
define void @i1_arg_sext_i64(i64 addrspace(1)* %out, i1 %x) nounwind {
%ext = sext i1 %x to i64
store i64 %ext, i64 addrspace(1)* %out, align 8
ret void
}