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https://github.com/c64scene-ar/llvm-6502.git
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e1274de2c9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11979 91177308-0d34-0410-b5e6-96231b3b80d8
108 lines
3.4 KiB
C++
108 lines
3.4 KiB
C++
//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SparcV8 implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8.h"
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#include "SparcV8RegisterInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Type.h"
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#include "Support/STLExtras.h"
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using namespace llvm;
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SparcV8RegisterInfo::SparcV8RegisterInfo()
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: SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
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V8::ADJCALLSTACKUP) {}
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int SparcV8RegisterInfo::storeRegToStackSlot(
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const
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{
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abort();
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return -1;
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}
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int SparcV8RegisterInfo::loadRegFromStackSlot(
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const
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{
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abort();
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return -1;
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}
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int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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abort();
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return -1;
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}
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void SparcV8RegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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abort();
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}
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void
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SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
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MachineBasicBlock::iterator II) const {
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abort();
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}
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void SparcV8RegisterInfo::
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processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
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void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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// Eventually this should emit the correct save instruction based on the
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// number of bytes in the frame. For now we just hardcode it.
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BuildMI(MBB, MBB.begin(), V8::SAVEi, 2, V8::SP).addImm(-122).addReg(V8::SP);
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}
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void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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assert(MBBI->getOpcode() == V8::JMPLi &&
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"Can only put epilog before return instruction!");
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BuildMI(MBB, MBBI, V8::RESTOREi, 2, V8::O0).addImm(0).addReg(V8::L7);
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}
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#include "SparcV8GenRegisterInfo.inc"
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const TargetRegisterClass*
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SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
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switch (Ty->getPrimitiveID()) {
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case Type::FloatTyID:
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case Type::DoubleTyID:
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assert(0 && "Floating point registers not supported yet!");
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case Type::LongTyID:
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case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
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default: assert(0 && "Invalid type to getClass!");
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case Type::BoolTyID:
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case Type::SByteTyID:
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case Type::UByteTyID:
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case Type::ShortTyID:
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case Type::UShortTyID:
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID: return &IntRegsInstance;
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}
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}
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