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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35600 91177308-0d34-0410-b5e6-96231b3b80d8
309 lines
11 KiB
C++
309 lines
11 KiB
C++
//===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass. Given some numbering of
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// each the machine instructions (in this implemention depth-first order) an
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// interval [i, j) is said to be a live interval for register v if there is no
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// instruction with number j' > j such that v is live at j' abd there is no
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// instruction with number i' < i such that v is live at i'. In this
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// implementation intervals can have holes, i.e. an interval might look like
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// [1,20), [50,65), [1000,1001).
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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#define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/IndexedMap.h"
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namespace llvm {
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class LiveVariables;
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class MRegisterInfo;
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class TargetInstrInfo;
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class VirtRegMap;
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class LiveIntervals : public MachineFunctionPass {
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MachineFunction* mf_;
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const TargetMachine* tm_;
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const MRegisterInfo* mri_;
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const TargetInstrInfo* tii_;
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LiveVariables* lv_;
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/// MBB2IdxMap - The index of the first instruction in the specified basic
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/// block.
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std::vector<unsigned> MBB2IdxMap;
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typedef std::map<MachineInstr*, unsigned> Mi2IndexMap;
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Mi2IndexMap mi2iMap_;
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typedef std::vector<MachineInstr*> Index2MiMap;
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Index2MiMap i2miMap_;
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typedef std::map<unsigned, LiveInterval> Reg2IntervalMap;
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Reg2IntervalMap r2iMap_;
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typedef IndexedMap<unsigned> Reg2RegMap;
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Reg2RegMap r2rMap_;
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BitVector allocatableRegs_;
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/// JoinedLIs - Keep track which register intervals have been coalesced
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/// with other intervals.
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BitVector JoinedLIs;
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public:
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struct CopyRec {
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MachineInstr *MI;
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unsigned SrcReg, DstReg;
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};
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CopyRec getCopyRec(MachineInstr *MI, unsigned SrcReg, unsigned DstReg) {
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CopyRec R;
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R.MI = MI;
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R.SrcReg = SrcReg;
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R.DstReg = DstReg;
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return R;
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}
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struct InstrSlots {
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enum {
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LOAD = 0,
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USE = 1,
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DEF = 2,
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STORE = 3,
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NUM = 4
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};
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};
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static unsigned getBaseIndex(unsigned index) {
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return index - (index % InstrSlots::NUM);
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}
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static unsigned getBoundaryIndex(unsigned index) {
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return getBaseIndex(index + InstrSlots::NUM - 1);
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}
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static unsigned getLoadIndex(unsigned index) {
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return getBaseIndex(index) + InstrSlots::LOAD;
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}
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static unsigned getUseIndex(unsigned index) {
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return getBaseIndex(index) + InstrSlots::USE;
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}
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static unsigned getDefIndex(unsigned index) {
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return getBaseIndex(index) + InstrSlots::DEF;
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}
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static unsigned getStoreIndex(unsigned index) {
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return getBaseIndex(index) + InstrSlots::STORE;
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}
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typedef Reg2IntervalMap::iterator iterator;
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typedef Reg2IntervalMap::const_iterator const_iterator;
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const_iterator begin() const { return r2iMap_.begin(); }
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const_iterator end() const { return r2iMap_.end(); }
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iterator begin() { return r2iMap_.begin(); }
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iterator end() { return r2iMap_.end(); }
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unsigned getNumIntervals() const { return r2iMap_.size(); }
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LiveInterval &getInterval(unsigned reg) {
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Reg2IntervalMap::iterator I = r2iMap_.find(reg);
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assert(I != r2iMap_.end() && "Interval does not exist for register");
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return I->second;
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}
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const LiveInterval &getInterval(unsigned reg) const {
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Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
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assert(I != r2iMap_.end() && "Interval does not exist for register");
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return I->second;
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}
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bool hasInterval(unsigned reg) const {
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return r2iMap_.count(reg);
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}
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/// getMBBStartIdx - Return the base index of the first instruction in the
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/// specified MachineBasicBlock.
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unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
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return getMBBStartIdx(MBB->getNumber());
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}
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unsigned getMBBStartIdx(unsigned MBBNo) const {
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assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
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return MBB2IdxMap[MBBNo];
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}
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/// getInstructionIndex - returns the base index of instr
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unsigned getInstructionIndex(MachineInstr* instr) const {
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Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
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assert(it != mi2iMap_.end() && "Invalid instruction!");
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return it->second;
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}
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/// getInstructionFromIndex - given an index in any slot of an
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/// instruction return a pointer the instruction
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MachineInstr* getInstructionFromIndex(unsigned index) const {
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index /= InstrSlots::NUM; // convert index to vector index
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assert(index < i2miMap_.size() &&
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"index does not correspond to an instruction");
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return i2miMap_[index];
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}
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std::vector<LiveInterval*> addIntervalsForSpills(const LiveInterval& i,
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VirtRegMap& vrm,
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int slot);
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/// CreateNewLiveInterval - Create a new live interval with the given live
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/// ranges. The new live interval will have an infinite spill weight.
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LiveInterval &CreateNewLiveInterval(const LiveInterval *LI,
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const std::vector<LiveRange> &LRs);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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/// runOnMachineFunction - pass entry point
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virtual bool runOnMachineFunction(MachineFunction&);
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/// print - Implement the dump method.
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virtual void print(std::ostream &O, const Module* = 0) const;
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void print(std::ostream *O, const Module* M = 0) const {
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if (O) print(*O, M);
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}
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private:
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/// isRemoved - returns true if the specified machine instr has been
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/// removed.
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bool isRemoved(MachineInstr* instr) const {
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return !mi2iMap_.count(instr);
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}
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/// RemoveMachineInstrFromMaps - This marks the specified machine instr as
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/// deleted.
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void RemoveMachineInstrFromMaps(MachineInstr *MI) {
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// remove index -> MachineInstr and
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// MachineInstr -> index mappings
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Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
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if (mi2i != mi2iMap_.end()) {
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i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
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mi2iMap_.erase(mi2i);
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}
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}
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/// computeIntervals - Compute live intervals.
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void computeIntervals();
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/// joinIntervals - join compatible live intervals
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void joinIntervals();
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/// CopyCoallesceInMBB - Coallsece copies in the specified MBB, putting
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/// copies that cannot yet be coallesced into the "TryAgain" list.
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void CopyCoallesceInMBB(MachineBasicBlock *MBB,
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std::vector<CopyRec> &TryAgain);
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/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
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/// which are the src/dst of the copy instruction CopyMI. This returns true
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/// if the copy was successfully coallesced away, or if it is never possible
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/// to coallesce these this copy, due to register constraints. It returns
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/// false if it is not currently possible to coallesce this interval, but
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/// it may be possible if other things get coallesced.
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bool JoinCopy(MachineInstr *CopyMI, unsigned SrcReg, unsigned DstReg);
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/// JoinIntervals - Attempt to join these two intervals. On failure, this
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/// returns false. Otherwise, if one of the intervals being joined is a
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/// physreg, this method always canonicalizes DestInt to be it. The output
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/// "SrcInt" will not have been modified, so we can use this information
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/// below to update aliases.
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bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS);
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/// SimpleJoin - Attempt to join the specified interval into this one. The
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/// caller of this method must guarantee that the RHS only contains a single
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/// value number and that the RHS is not defined by a copy from this
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/// interval. This returns false if the intervals are not joinable, or it
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/// joins them and returns true.
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bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS);
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/// handleRegisterDef - update intervals for a register def
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/// (calls handlePhysicalRegisterDef and
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/// handleVirtualRegisterDef)
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void handleRegisterDef(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI, unsigned MIIdx,
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unsigned reg);
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/// handleVirtualRegisterDef - update intervals for a virtual
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/// register def
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void handleVirtualRegisterDef(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI,
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unsigned MIIdx,
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LiveInterval& interval);
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/// handlePhysicalRegisterDef - update intervals for a physical register
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/// def.
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void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
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MachineBasicBlock::iterator mi,
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unsigned MIIdx,
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LiveInterval &interval,
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unsigned SrcReg);
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/// handleLiveInRegister - Create interval for a livein register.
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void handleLiveInRegister(MachineBasicBlock* mbb,
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unsigned MIIdx,
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LiveInterval &interval);
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/// Return true if the two specified registers belong to different
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/// register classes. The registers may be either phys or virt regs.
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bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
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bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
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MachineInstr *CopyMI);
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/// lastRegisterUse - Returns the last use of the specific register between
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/// cycles Start and End. It also returns the use operand by reference. It
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/// returns NULL if there are no uses.
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MachineInstr *lastRegisterUse(unsigned Reg, unsigned Start, unsigned End,
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MachineOperand *&MOU);
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/// findDefOperand - Returns the MachineOperand that is a def of the specific
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/// register. It returns NULL if the def is not found.
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MachineOperand *findDefOperand(MachineInstr *MI, unsigned Reg);
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/// unsetRegisterKill - Unset IsKill property of all uses of the specific
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/// register of the specific instruction.
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void unsetRegisterKill(MachineInstr *MI, unsigned Reg);
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/// hasRegisterDef - True if the instruction defines the specific register.
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///
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bool hasRegisterDef(MachineInstr *MI, unsigned Reg);
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static LiveInterval createInterval(unsigned Reg);
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void removeInterval(unsigned Reg) {
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r2iMap_.erase(Reg);
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}
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LiveInterval &getOrCreateInterval(unsigned reg) {
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Reg2IntervalMap::iterator I = r2iMap_.find(reg);
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if (I == r2iMap_.end())
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I = r2iMap_.insert(I, std::make_pair(reg, createInterval(reg)));
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return I->second;
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}
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/// rep - returns the representative of this register
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unsigned rep(unsigned Reg) {
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unsigned Rep = r2rMap_[Reg];
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if (Rep)
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return r2rMap_[Reg] = rep(Rep);
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return Reg;
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}
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void printRegName(unsigned reg) const;
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};
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} // End llvm namespace
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#endif
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