mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 16:29:20 +00:00
ff8d7fb136
Setting vector types to expand will result in scalarization on pre SI hw,
as those gpus don't have vector shifts either.
Expand also i32 vectors, this helps llvm make the correct decision
about scalarizing the vector ops.
v2: move setOperation() calls to R600ISelLowering.cpp.
cleanup the SI code to make it obvious that this patch does is nop for SI
Patch by: Jan Vesely <jan.vesely@rutgers.edu>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206348 91177308-0d34-0410-b5e6-96231b3b80d8
595 lines
18 KiB
TableGen
595 lines
18 KiB
TableGen
//===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// TableGen definitions for instructions which are:
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// - Available to Evergreen and newer VLIW4/VLIW5 GPUs
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// - Available only on Evergreen family GPUs.
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//
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//===----------------------------------------------------------------------===//
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def isEG : Predicate<
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"Subtarget.getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
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"Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && "
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"!Subtarget.hasCaymanISA()"
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>;
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def isEGorCayman : Predicate<
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"Subtarget.getGeneration() == AMDGPUSubtarget::EVERGREEN ||"
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"Subtarget.getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS"
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>;
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//===----------------------------------------------------------------------===//
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// Evergreen / Cayman store instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [isEGorCayman] in {
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class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,
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string name, list<dag> pattern>
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: EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins,
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"MEM_RAT_CACHELESS "#name, pattern>;
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class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, dag ins, string name,
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list<dag> pattern>
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: EG_CF_RAT <0x56, rat_inst, rat_id, 0xf /* mask */, (outs), ins,
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"MEM_RAT "#name, pattern>;
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def RAT_MSKOR : CF_MEM_RAT <0x11, 0,
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(ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
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"MSKOR $rw_gpr.XW, $index_gpr",
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[(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]
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> {
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let eop = 0;
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}
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} // End let Predicates = [isEGorCayman]
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//===----------------------------------------------------------------------===//
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// Evergreen Only instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [isEG] in {
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def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
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defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
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def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
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def MULHI_INT_eg : MULHI_INT_Common<0x90>;
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def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
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def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
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def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
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def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
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def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
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def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
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def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
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def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
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def SIN_eg : SIN_Common<0x8D>;
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def COS_eg : COS_Common<0x8E>;
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def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
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def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
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//===----------------------------------------------------------------------===//
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// Memory read/write instructions
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//===----------------------------------------------------------------------===//
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let usesCustomInserter = 1 in {
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// 32-bit store
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def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1,
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(ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
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"STORE_RAW $rw_gpr, $index_gpr, $eop",
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[(global_store i32:$rw_gpr, i32:$index_gpr)]
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>;
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// 64-bit store
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def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3,
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(ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
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"STORE_RAW $rw_gpr.XY, $index_gpr, $eop",
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[(global_store v2i32:$rw_gpr, i32:$index_gpr)]
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>;
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//128-bit store
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def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf,
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(ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
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"STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop",
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[(global_store v4i32:$rw_gpr, i32:$index_gpr)]
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>;
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} // End usesCustomInserter = 1
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class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
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: VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> {
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// Static fields
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let VC_INST = 0;
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let FETCH_TYPE = 2;
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let FETCH_WHOLE_QUAD = 0;
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let BUFFER_ID = buffer_id;
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let SRC_REL = 0;
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// XXX: We can infer this field based on the SRC_GPR. This would allow us
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// to store vertex addresses in any channel, not just X.
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let SRC_SEL_X = 0;
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let Inst{31-0} = Word0;
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}
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class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
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: VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
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(outs R600_TReg32_X:$dst_gpr), pattern> {
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let MEGA_FETCH_COUNT = 1;
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let DST_SEL_X = 0;
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let DST_SEL_Y = 7; // Masked
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let DST_SEL_Z = 7; // Masked
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let DST_SEL_W = 7; // Masked
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let DATA_FORMAT = 1; // FMT_8
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}
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class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
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: VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
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(outs R600_TReg32_X:$dst_gpr), pattern> {
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let MEGA_FETCH_COUNT = 2;
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let DST_SEL_X = 0;
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let DST_SEL_Y = 7; // Masked
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let DST_SEL_Z = 7; // Masked
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let DST_SEL_W = 7; // Masked
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let DATA_FORMAT = 5; // FMT_16
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}
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class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
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: VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
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(outs R600_TReg32_X:$dst_gpr), pattern> {
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let MEGA_FETCH_COUNT = 4;
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let DST_SEL_X = 0;
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let DST_SEL_Y = 7; // Masked
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let DST_SEL_Z = 7; // Masked
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let DST_SEL_W = 7; // Masked
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let DATA_FORMAT = 0xD; // COLOR_32
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// This is not really necessary, but there were some GPU hangs that appeared
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// to be caused by ALU instructions in the next instruction group that wrote
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// to the $src_gpr registers of the VTX_READ.
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// e.g.
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// %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
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// %T2_X<def> = MOV %ZERO
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//Adding this constraint prevents this from happening.
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let Constraints = "$src_gpr.ptr = $dst_gpr";
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}
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class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern>
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: VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", buffer_id,
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(outs R600_Reg64:$dst_gpr), pattern> {
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let MEGA_FETCH_COUNT = 8;
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let DST_SEL_X = 0;
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let DST_SEL_Y = 1;
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let DST_SEL_Z = 7;
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let DST_SEL_W = 7;
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let DATA_FORMAT = 0x1D; // COLOR_32_32
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}
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class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
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: VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
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(outs R600_Reg128:$dst_gpr), pattern> {
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let MEGA_FETCH_COUNT = 16;
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let DST_SEL_X = 0;
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let DST_SEL_Y = 1;
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let DST_SEL_Z = 2;
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let DST_SEL_W = 3;
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let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
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// XXX: Need to force VTX_READ_128 instructions to write to the same register
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// that holds its buffer address to avoid potential hangs. We can't use
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// the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
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// registers are different sizes.
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}
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//===----------------------------------------------------------------------===//
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// VTX Read from parameter memory space
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//===----------------------------------------------------------------------===//
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def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
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[(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
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>;
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def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
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[(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
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>;
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def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
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[(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
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>;
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def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <0,
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[(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
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>;
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def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
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[(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
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>;
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//===----------------------------------------------------------------------===//
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// VTX Read from global memory space
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//===----------------------------------------------------------------------===//
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// 8-bit reads
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def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
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[(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
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>;
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def VTX_READ_GLOBAL_16_eg : VTX_READ_16_eg <1,
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[(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
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>;
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// 32-bit reads
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def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
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[(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
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>;
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// 64-bit reads
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def VTX_READ_GLOBAL_64_eg : VTX_READ_64_eg <1,
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[(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
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>;
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// 128-bit reads
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def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
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[(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
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>;
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} // End Predicates = [isEG]
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//===----------------------------------------------------------------------===//
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// Evergreen / Cayman Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [isEGorCayman] in {
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// BFE_UINT - bit_extract, an optimization for mask and shift
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// Src0 = Input
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// Src1 = Offset
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// Src2 = Width
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//
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// bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
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//
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// Example Usage:
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// (Offset, Width)
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//
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// (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
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// (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
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// (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
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// (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
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def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
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[(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
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VecALU
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>;
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def BFE_INT_eg : R600_3OP <0x5, "BFE_INT",
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[(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
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VecALU
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>;
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// XXX: This pattern is broken, disabling for now. See comment in
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// AMDGPUInstructions.td for more info.
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// def : BFEPattern <BFE_UINT_eg>;
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def BFI_INT_eg : R600_3OP <0x06, "BFI_INT",
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[(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
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VecALU
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>;
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def : Pat<(i32 (sext_inreg i32:$src, i1)),
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(BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>;
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def : Pat<(i32 (sext_inreg i32:$src, i8)),
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(BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>;
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def : Pat<(i32 (sext_inreg i32:$src, i16)),
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(BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>;
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defm : BFIPatterns <BFI_INT_eg>;
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def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT",
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[(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))],
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VecALU
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>;
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def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",
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[(set i32:$dst, (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2))], VecALU
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>;
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def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
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def : ROTRPattern <BIT_ALIGN_INT_eg>;
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def MULADD_eg : MULADD_Common<0x14>;
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def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
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def ASHR_eg : ASHR_Common<0x15>;
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def LSHR_eg : LSHR_Common<0x16>;
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def LSHL_eg : LSHL_Common<0x17>;
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def CNDE_eg : CNDE_Common<0x19>;
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def CNDGT_eg : CNDGT_Common<0x1A>;
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def CNDGE_eg : CNDGE_Common<0x1B>;
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def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
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def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
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def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24",
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[(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU
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>;
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def DOT4_eg : DOT4_Common<0xBE>;
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defm CUBE_eg : CUBE_Common<0xC0>;
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let hasSideEffects = 1 in {
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def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>;
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}
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def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
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def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
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let Pattern = [];
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let Itinerary = AnyALU;
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}
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def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
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def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
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let Pattern = [];
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}
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def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
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def GROUP_BARRIER : InstR600 <
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(outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local)], AnyALU>,
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R600ALU_Word0,
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R600ALU_Word1_OP2 <0x54> {
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let dst = 0;
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let dst_rel = 0;
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let src0 = 0;
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let src0_rel = 0;
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let src0_neg = 0;
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let src0_abs = 0;
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let src1 = 0;
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let src1_rel = 0;
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let src1_neg = 0;
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let src1_abs = 0;
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let write = 0;
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let omod = 0;
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let clamp = 0;
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let last = 1;
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let bank_swizzle = 0;
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let pred_sel = 0;
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let update_exec_mask = 0;
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let update_pred = 0;
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let Inst{31-0} = Word0;
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let Inst{63-32} = Word1;
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let ALUInst = 1;
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}
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//===----------------------------------------------------------------------===//
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// LDS Instructions
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//===----------------------------------------------------------------------===//
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class R600_LDS <bits<6> op, dag outs, dag ins, string asm,
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list<dag> pattern = []> :
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InstR600 <outs, ins, asm, pattern, XALU>,
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R600_ALU_LDS_Word0,
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R600LDS_Word1 {
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bits<6> offset = 0;
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let lds_op = op;
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let Word1{27} = offset{0};
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let Word1{12} = offset{1};
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let Word1{28} = offset{2};
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let Word1{31} = offset{3};
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let Word0{12} = offset{4};
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let Word0{25} = offset{5};
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let Inst{31-0} = Word0;
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let Inst{63-32} = Word1;
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let ALUInst = 1;
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let HasNativeOperands = 1;
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let UseNamedOperandTable = 1;
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}
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class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
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lds_op,
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(outs R600_Reg32:$dst),
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(ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
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LAST:$last, R600_Pred:$pred_sel,
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BANK_SWIZZLE:$bank_swizzle),
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" "#name#" $last OQAP, $src0$src0_rel $pred_sel",
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pattern
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> {
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let src1 = 0;
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let src1_rel = 0;
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let src2 = 0;
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let src2_rel = 0;
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let usesCustomInserter = 1;
|
|
let LDS_1A = 1;
|
|
let DisableEncoding = "$dst";
|
|
}
|
|
|
|
class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
|
|
string dst =""> :
|
|
R600_LDS <
|
|
lds_op, outs,
|
|
(ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
|
|
R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
|
|
LAST:$last, R600_Pred:$pred_sel,
|
|
BANK_SWIZZLE:$bank_swizzle),
|
|
" "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel",
|
|
pattern
|
|
> {
|
|
|
|
field string BaseOp;
|
|
|
|
let src2 = 0;
|
|
let src2_rel = 0;
|
|
let LDS_1A1D = 1;
|
|
}
|
|
|
|
class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
|
|
R600_LDS_1A1D <lds_op, (outs), name, pattern> {
|
|
let BaseOp = name;
|
|
}
|
|
|
|
class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> :
|
|
R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> {
|
|
|
|
let BaseOp = name;
|
|
let usesCustomInserter = 1;
|
|
let DisableEncoding = "$dst";
|
|
}
|
|
|
|
class R600_LDS_1A2D <bits<6> lds_op, string name, list<dag> pattern> :
|
|
R600_LDS <
|
|
lds_op,
|
|
(outs),
|
|
(ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
|
|
R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
|
|
R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel,
|
|
LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
|
|
" "#name# "$last $src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
|
|
pattern> {
|
|
let LDS_1A2D = 1;
|
|
}
|
|
|
|
def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >;
|
|
def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >;
|
|
def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE",
|
|
[(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)]
|
|
>;
|
|
def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE",
|
|
[(truncstorei8_local i32:$src1, i32:$src0)]
|
|
>;
|
|
def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE",
|
|
[(truncstorei16_local i32:$src1, i32:$src0)]
|
|
>;
|
|
def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD",
|
|
[(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))]
|
|
>;
|
|
def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB",
|
|
[(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))]
|
|
>;
|
|
def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",
|
|
[(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))]
|
|
>;
|
|
def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET",
|
|
[(set i32:$dst, (sextloadi8_local i32:$src0))]
|
|
>;
|
|
def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET",
|
|
[(set i32:$dst, (az_extloadi8_local i32:$src0))]
|
|
>;
|
|
def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET",
|
|
[(set i32:$dst, (sextloadi16_local i32:$src0))]
|
|
>;
|
|
def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET",
|
|
[(set i32:$dst, (az_extloadi16_local i32:$src0))]
|
|
>;
|
|
|
|
// TRUNC is used for the FLT_TO_INT instructions to work around a
|
|
// perceived problem where the rounding modes are applied differently
|
|
// depending on the instruction and the slot they are in.
|
|
// See:
|
|
// https://bugs.freedesktop.org/show_bug.cgi?id=50232
|
|
// Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
|
|
//
|
|
// XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
|
|
// which do not need to be truncated since the fp values are 0.0f or 1.0f.
|
|
// We should look into handling these cases separately.
|
|
def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
|
|
|
|
def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
|
|
|
|
// SHA-256 Patterns
|
|
def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
|
|
|
|
def : FROUNDPat <CNDGE_eg>;
|
|
|
|
def EG_ExportSwz : ExportSwzInst {
|
|
let Word1{19-16} = 0; // BURST_COUNT
|
|
let Word1{20} = 0; // VALID_PIXEL_MODE
|
|
let Word1{21} = eop;
|
|
let Word1{29-22} = inst;
|
|
let Word1{30} = 0; // MARK
|
|
let Word1{31} = 1; // BARRIER
|
|
}
|
|
defm : ExportPattern<EG_ExportSwz, 83>;
|
|
|
|
def EG_ExportBuf : ExportBufInst {
|
|
let Word1{19-16} = 0; // BURST_COUNT
|
|
let Word1{20} = 0; // VALID_PIXEL_MODE
|
|
let Word1{21} = eop;
|
|
let Word1{29-22} = inst;
|
|
let Word1{30} = 0; // MARK
|
|
let Word1{31} = 1; // BARRIER
|
|
}
|
|
defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
|
|
|
|
def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
|
|
"TEX $COUNT @$ADDR"> {
|
|
let POP_COUNT = 0;
|
|
}
|
|
def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
|
|
"VTX $COUNT @$ADDR"> {
|
|
let POP_COUNT = 0;
|
|
}
|
|
def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
|
|
"LOOP_START_DX10 @$ADDR"> {
|
|
let POP_COUNT = 0;
|
|
let COUNT = 0;
|
|
}
|
|
def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
|
|
let POP_COUNT = 0;
|
|
let COUNT = 0;
|
|
}
|
|
def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
|
|
"LOOP_BREAK @$ADDR"> {
|
|
let POP_COUNT = 0;
|
|
let COUNT = 0;
|
|
}
|
|
def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
|
|
"CONTINUE @$ADDR"> {
|
|
let POP_COUNT = 0;
|
|
let COUNT = 0;
|
|
}
|
|
def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
|
|
"JUMP @$ADDR POP:$POP_COUNT"> {
|
|
let COUNT = 0;
|
|
}
|
|
def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
|
|
"PUSH @$ADDR POP:$POP_COUNT"> {
|
|
let COUNT = 0;
|
|
}
|
|
def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
|
|
"ELSE @$ADDR POP:$POP_COUNT"> {
|
|
let COUNT = 0;
|
|
}
|
|
def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
|
|
let ADDR = 0;
|
|
let COUNT = 0;
|
|
let POP_COUNT = 0;
|
|
}
|
|
def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
|
|
"POP @$ADDR POP:$POP_COUNT"> {
|
|
let COUNT = 0;
|
|
}
|
|
def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
|
|
let COUNT = 0;
|
|
let POP_COUNT = 0;
|
|
let ADDR = 0;
|
|
let END_OF_PROGRAM = 1;
|
|
}
|
|
|
|
} // End Predicates = [isEGorCayman]
|