llvm-6502/lib/Target/PowerPC/PowerPCInstrInfo.cpp
Misha Brukman 3ada3e3f82 ADDI can take several forms, including:
addi r1, r2, 0
  addi r1, <frame index #n>, 0

so we must check for the second parameter being a register for this instruction
to be considered a reg-to-reg copy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15244 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-26 21:50:38 +00:00

61 lines
2.3 KiB
C++

//===- PowerPCInstrInfo.cpp - PowerPC Instruction Information ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#include "PowerPCInstrInfo.h"
#include "PowerPC.h"
#include "PowerPCGenInstrInfo.inc"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include <iostream>
using namespace llvm;
PowerPCInstrInfo::PowerPCInstrInfo()
: TargetInstrInfo(PowerPCInsts, sizeof(PowerPCInsts)/sizeof(PowerPCInsts[0]))
{ }
bool PowerPCInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
if (oc == PPC32::OR) { // or r1, r2, r2
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isRegister() &&
"invalid PPC32 OR instruction!");
if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC32::ADDI) { // addi r1, r2, 0
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(2).isImmediate() &&
"invalid PPC32 ADDI instruction!");
if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC32::FMR) { // fmr r1, r2
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"invalid PPC32 FMR instruction");
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
return false;
}