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bd5cafd9bb
The PPC target feature gpul (IsGigaProcessor) was only used for one thing: To enable the generation of the MFOCRF instruction. Furthermore, this instruction is available on other PPC cores outside of the G5 line. This feature now corresponds to the HasMFOCRF flag. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158323 91177308-0d34-0410-b5e6-96231b3b80d8
133 lines
6.3 KiB
TableGen
133 lines
6.3 KiB
TableGen
//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the top level entry point for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing.
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//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// PowerPC Subtarget features.
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//
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//===----------------------------------------------------------------------===//
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// CPU Directives //
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//===----------------------------------------------------------------------===//
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def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
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def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
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def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
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def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
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def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
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def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
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def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
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def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
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def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
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def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
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def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
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def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
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def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
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def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
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def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
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"Enable 64-bit instructions">;
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def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
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"Enable 64-bit registers usage for ppc32 [beta]">;
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def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
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"Enable Altivec instructions">;
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def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
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"Enable the MFOCRF instruction">;
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def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
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"Enable the fsqrt instruction">;
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def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
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"Enable the stfiwx instruction">;
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def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
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"Enable Book E instructions">;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "PPCRegisterInfo.td"
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include "PPCSchedule.td"
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include "PPCInstrInfo.td"
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//===----------------------------------------------------------------------===//
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// PowerPC processors supported.
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//
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def : Processor<"generic", G3Itineraries, [Directive32]>;
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def : Processor<"440", PPC440Itineraries, [Directive440, FeatureBookE]>;
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def : Processor<"450", PPC440Itineraries, [Directive440, FeatureBookE]>;
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def : Processor<"601", G3Itineraries, [Directive601]>;
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def : Processor<"602", G3Itineraries, [Directive602]>;
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def : Processor<"603", G3Itineraries, [Directive603]>;
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def : Processor<"603e", G3Itineraries, [Directive603]>;
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def : Processor<"603ev", G3Itineraries, [Directive603]>;
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def : Processor<"604", G3Itineraries, [Directive604]>;
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def : Processor<"604e", G3Itineraries, [Directive604]>;
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def : Processor<"620", G3Itineraries, [Directive620]>;
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def : Processor<"g3", G3Itineraries, [Directive7400]>;
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def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
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def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
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def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
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def : Processor<"g4+", G4PlusItineraries, [Directive750, FeatureAltivec]>;
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def : Processor<"750", G4Itineraries, [Directive750, FeatureAltivec]>;
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def : Processor<"970", G5Itineraries,
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[Directive970, FeatureAltivec,
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FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
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Feature64Bit /*, Feature64BitRegs */]>;
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def : Processor<"g5", G5Itineraries,
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[Directive970, FeatureAltivec,
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FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
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Feature64Bit /*, Feature64BitRegs */]>;
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def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
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FeatureFSqrt, FeatureSTFIWX,
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Feature64Bit
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/*, Feature64BitRegs */]>;
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def : Processor<"pwr6", G5Itineraries,
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[DirectivePwr6, FeatureAltivec,
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FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
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Feature64Bit /*, Feature64BitRegs */]>;
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def : Processor<"pwr7", G5Itineraries,
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[DirectivePwr7, FeatureAltivec,
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FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
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Feature64Bit /*, Feature64BitRegs */]>;
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def : Processor<"ppc", G3Itineraries, [Directive32]>;
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def : Processor<"ppc64", G5Itineraries,
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[Directive64, FeatureAltivec,
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FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
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Feature64Bit /*, Feature64BitRegs */]>;
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//===----------------------------------------------------------------------===//
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// Calling Conventions
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//===----------------------------------------------------------------------===//
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include "PPCCallingConv.td"
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def PPCInstrInfo : InstrInfo {
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let isLittleEndianEncoding = 1;
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}
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def PPCAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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bit isMCAsmWriter = 1;
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}
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def PPC : Target {
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// Information about the instructions.
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let InstructionSet = PPCInstrInfo;
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let AssemblyWriters = [PPCAsmWriter];
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}
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