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72062f5744
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.
This initial commit should have support for:
+ Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
(except the late addition CRC instructions).
+ CodeGen features required for C++03 and C99.
+ Compilation for the "small" memory model: code+static data <
4GB.
+ Absolute and position-independent code.
+ GNU-style (i.e. "__thread") TLS.
+ Debugging information.
The principal omission, currently, is performance tuning.
This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.
Further reviews would be gratefully received.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
18 lines
498 B
Plaintext
18 lines
498 B
Plaintext
# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s
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# None of these instructions should be classified as unpredictable:
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# CHECK-NOT: potentially undefined instruction encoding
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# Stores from duplicated registers should be fine.
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0xe3 0x0f 0x80 0xa8
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# CHECK: stp x3, x3, [sp], #0
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# d5 != x5 so "ldp d5, d6, [x5], #24" is fine.
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0xa5 0x98 0xc1 0x6c
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# CHECK: ldp d5, d6, [x5], #24
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# xzr != sp so "stp xzr, xzr, [sp], #8" is fine.
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0xff 0xff 0x80 0xa8
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# CHECK: stp xzr, xzr, [sp], #8
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