llvm-6502/test/CodeGen
Dale Johannesen bdc09d9b09 The SelectionDAGBuilder's handling of debug info, on rare
occasions, caused code to be generated in a different order.
All cases I've seen involved float softening in the type
legalizer, and this could be perhaps be fixed there, but
it's better not to generate things differently in the first
place.  7797940 (6/29/2010..7/15/2010).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108484 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 00:02:08 +00:00
..
Alpha
ARM Split -enable-finite-only-fp-math to two options: 2010-07-15 22:07:12 +00:00
Blackfin Remove TargetInstrInfo::copyRegToReg entirely. 2010-07-11 17:01:17 +00:00
CBackend
CellSPU
CPP
Generic Fix up -fstack-protector on linux to use the segment 2010-07-06 05:18:56 +00:00
MBlaze
Mips
MSP430
PIC16
PowerPC Revert. This isn't the correct way to go. 2010-07-15 23:42:21 +00:00
SPARC
SystemZ
Thumb The SelectionDAGBuilder's handling of debug info, on rare 2010-07-16 00:02:08 +00:00
Thumb2 Improve 64-subtraction of immediates when parts of the immediate can fit 2010-07-14 17:45:16 +00:00
X86 Revert. This isn't the correct way to go. 2010-07-15 23:42:21 +00:00
XCore