mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2bce5f4b56
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
218 lines
5.4 KiB
LLVM
218 lines
5.4 KiB
LLVM
; RUN: llc < %s -march=x86-64 | FileCheck %s
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; rdar://7103704
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define void @sub1(i32* nocapture %p, i32 %v) nounwind ssp {
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entry:
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; CHECK: sub1:
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; CHECK: subl
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%0 = tail call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %p, i32 %v) ; <i32> [#uses=0]
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ret void
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}
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define void @inc4(i64* nocapture %p) nounwind ssp {
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entry:
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; CHECK: inc4:
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; CHECK: incq
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%0 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 1) ; <i64> [#uses=0]
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ret void
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}
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declare i64 @llvm.atomic.load.add.i64.p0i64(i64* nocapture, i64) nounwind
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define void @add8(i64* nocapture %p) nounwind ssp {
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entry:
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; CHECK: add8:
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; CHECK: addq $2
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%0 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 2) ; <i64> [#uses=0]
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ret void
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}
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define void @add4(i64* nocapture %p, i32 %v) nounwind ssp {
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entry:
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; CHECK: add4:
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; CHECK: addq
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%0 = sext i32 %v to i64 ; <i64> [#uses=1]
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%1 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 %0) ; <i64> [#uses=0]
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ret void
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}
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define void @inc3(i8* nocapture %p) nounwind ssp {
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entry:
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; CHECK: inc3:
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; CHECK: incb
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%0 = tail call i8 @llvm.atomic.load.add.i8.p0i8(i8* %p, i8 1) ; <i8> [#uses=0]
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ret void
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}
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declare i8 @llvm.atomic.load.add.i8.p0i8(i8* nocapture, i8) nounwind
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define void @add7(i8* nocapture %p) nounwind ssp {
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entry:
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; CHECK: add7:
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; CHECK: addb $2
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%0 = tail call i8 @llvm.atomic.load.add.i8.p0i8(i8* %p, i8 2) ; <i8> [#uses=0]
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ret void
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}
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define void @add3(i8* nocapture %p, i32 %v) nounwind ssp {
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entry:
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; CHECK: add3:
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; CHECK: addb
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%0 = trunc i32 %v to i8 ; <i8> [#uses=1]
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%1 = tail call i8 @llvm.atomic.load.add.i8.p0i8(i8* %p, i8 %0) ; <i8> [#uses=0]
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ret void
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}
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define void @inc2(i16* nocapture %p) nounwind ssp {
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entry:
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; CHECK: inc2:
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; CHECK: incw
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%0 = tail call i16 @llvm.atomic.load.add.i16.p0i16(i16* %p, i16 1) ; <i16> [#uses=0]
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ret void
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}
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declare i16 @llvm.atomic.load.add.i16.p0i16(i16* nocapture, i16) nounwind
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define void @add6(i16* nocapture %p) nounwind ssp {
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entry:
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; CHECK: add6:
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; CHECK: addw $2
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%0 = tail call i16 @llvm.atomic.load.add.i16.p0i16(i16* %p, i16 2) ; <i16> [#uses=0]
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ret void
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}
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define void @add2(i16* nocapture %p, i32 %v) nounwind ssp {
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entry:
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; CHECK: add2:
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; CHECK: addw
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%0 = trunc i32 %v to i16 ; <i16> [#uses=1]
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%1 = tail call i16 @llvm.atomic.load.add.i16.p0i16(i16* %p, i16 %0) ; <i16> [#uses=0]
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ret void
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}
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define void @inc1(i32* nocapture %p) nounwind ssp {
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entry:
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; CHECK: inc1:
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; CHECK: incl
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%0 = tail call i32 @llvm.atomic.load.add.i32.p0i32(i32* %p, i32 1) ; <i32> [#uses=0]
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ret void
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}
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declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind
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define void @add5(i32* nocapture %p) nounwind ssp {
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entry:
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; CHECK: add5:
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; CHECK: addl $2
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%0 = tail call i32 @llvm.atomic.load.add.i32.p0i32(i32* %p, i32 2) ; <i32> [#uses=0]
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ret void
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}
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define void @add1(i32* nocapture %p, i32 %v) nounwind ssp {
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entry:
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; CHECK: add1:
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; CHECK: addl
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%0 = tail call i32 @llvm.atomic.load.add.i32.p0i32(i32* %p, i32 %v) ; <i32> [#uses=0]
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ret void
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}
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define void @dec4(i64* nocapture %p) nounwind ssp {
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entry:
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; CHECK: dec4:
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; CHECK: decq
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%0 = tail call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %p, i64 1) ; <i64> [#uses=0]
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ret void
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}
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declare i64 @llvm.atomic.load.sub.i64.p0i64(i64* nocapture, i64) nounwind
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define void @sub8(i64* nocapture %p) nounwind ssp {
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entry:
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; CHECK: sub8:
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; CHECK: subq $2
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%0 = tail call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %p, i64 2) ; <i64> [#uses=0]
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ret void
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}
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define void @sub4(i64* nocapture %p, i32 %v) nounwind ssp {
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entry:
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; CHECK: sub4:
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; CHECK: subq
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%0 = sext i32 %v to i64 ; <i64> [#uses=1]
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%1 = tail call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %p, i64 %0) ; <i64> [#uses=0]
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ret void
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}
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define void @dec3(i8* nocapture %p) nounwind ssp {
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entry:
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; CHECK: dec3:
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; CHECK: decb
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%0 = tail call i8 @llvm.atomic.load.sub.i8.p0i8(i8* %p, i8 1) ; <i8> [#uses=0]
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ret void
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}
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declare i8 @llvm.atomic.load.sub.i8.p0i8(i8* nocapture, i8) nounwind
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define void @sub7(i8* nocapture %p) nounwind ssp {
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entry:
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; CHECK: sub7:
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; CHECK: subb $2
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%0 = tail call i8 @llvm.atomic.load.sub.i8.p0i8(i8* %p, i8 2) ; <i8> [#uses=0]
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ret void
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}
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define void @sub3(i8* nocapture %p, i32 %v) nounwind ssp {
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entry:
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; CHECK: sub3:
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; CHECK: subb
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%0 = trunc i32 %v to i8 ; <i8> [#uses=1]
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%1 = tail call i8 @llvm.atomic.load.sub.i8.p0i8(i8* %p, i8 %0) ; <i8> [#uses=0]
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ret void
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}
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define void @dec2(i16* nocapture %p) nounwind ssp {
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entry:
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; CHECK: dec2:
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; CHECK: decw
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%0 = tail call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %p, i16 1) ; <i16> [#uses=0]
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ret void
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}
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declare i16 @llvm.atomic.load.sub.i16.p0i16(i16* nocapture, i16) nounwind
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define void @sub6(i16* nocapture %p) nounwind ssp {
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entry:
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; CHECK: sub6:
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; CHECK: subw $2
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%0 = tail call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %p, i16 2) ; <i16> [#uses=0]
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ret void
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}
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define void @sub2(i16* nocapture %p, i32 %v) nounwind ssp {
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entry:
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; CHECK: sub2:
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; CHECK: negl
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%0 = trunc i32 %v to i16 ; <i16> [#uses=1]
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%1 = tail call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %p, i16 %0) ; <i16> [#uses=0]
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ret void
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}
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define void @dec1(i32* nocapture %p) nounwind ssp {
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entry:
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; CHECK: dec1:
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; CHECK: decl
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%0 = tail call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %p, i32 1) ; <i32> [#uses=0]
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ret void
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}
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declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* nocapture, i32) nounwind
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define void @sub5(i32* nocapture %p) nounwind ssp {
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entry:
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; CHECK: sub5:
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; CHECK: subl $2
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%0 = tail call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %p, i32 2) ; <i32> [#uses=0]
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ret void
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}
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