llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-30 02:32:08 +00:00

History

Chris Lattner 2adc05cf5b Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure from last night git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25819 91177308-0d34-0410-b5e6-96231b3b80d8		2006-01-30 22:20:49 +00:00
..
.cvsignore
DelaySlotFiller.cpp
FPMover.cpp	If the target has V9 instructions, this pass is a noop, don't bother	2006-01-30 05:51:14 +00:00
Makefile
README.txt	First step towards V9 instructions in the V8 backend, two conditional move	2006-01-30 05:35:57 +00:00
SparcV8.h
SparcV8.td
SparcV8AsmPrinter.cpp
SparcV8InstrFormats.td
SparcV8InstrInfo.cpp
SparcV8InstrInfo.h
SparcV8InstrInfo.td	Revamp the ICC/FCC reading instructions to be parameterized in terms of the	2006-01-30 07:43:04 +00:00
SparcV8ISelDAGToDAG.cpp	Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure from last night	2006-01-30 22:20:49 +00:00
SparcV8RegisterInfo.cpp
SparcV8RegisterInfo.h
SparcV8RegisterInfo.td
SparcV8Subtarget.cpp	Two changes:	2006-01-30 04:57:43 +00:00
SparcV8Subtarget.h
SparcV8TargetMachine.cpp
SparcV8TargetMachine.h

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].