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be02a90de1
- Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
33 lines
1.2 KiB
TableGen
33 lines
1.2 KiB
TableGen
//===-- X86InstrVMX.td - TSX Instruction Set Extension -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the Intel TSX instruction
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// set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// TSX instructions
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let usesCustomInserter = 1 in
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def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
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"# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>,
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Requires<[HasRTM]>;
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let isBranch = 1, isTerminator = 1, Defs = [EAX] in
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def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget:$dst),
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"xbegin\t$dst", []>;
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def XEND : I<0x01, MRM_D5, (outs), (ins),
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"xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
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def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm),
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"xabort\t$imm",
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[(int_x86_xabort imm:$imm)]>, Requires<[HasRTM]>;
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