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d4f759696d
any scheduling heuristics nor does it build up any scheduling data structure that other heuristics use. It essentially linearize by doing a DFA walk but it does handle glues correctly. IMPORTANT: it probably can't handle all the physical register dependencies so it's not suitable for x86. It also doesn't deal with dbg_value nodes right now so it's definitely is still WIP. rdar://12474515 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166122 91177308-0d34-0410-b5e6-96231b3b80d8
113 lines
4.3 KiB
C++
113 lines
4.3 KiB
C++
//===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation for instruction scheduler function
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// pass registry (RegisterScheduler).
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGENSCHEDULERREGISTRY_H
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#define LLVM_CODEGENSCHEDULERREGISTRY_H
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#include "llvm/CodeGen/MachinePassRegistry.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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//===----------------------------------------------------------------------===//
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///
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/// RegisterScheduler class - Track the registration of instruction schedulers.
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///
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//===----------------------------------------------------------------------===//
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class SelectionDAGISel;
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class ScheduleDAGSDNodes;
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class SelectionDAG;
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class MachineBasicBlock;
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class RegisterScheduler : public MachinePassRegistryNode {
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public:
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typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
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CodeGenOpt::Level);
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static MachinePassRegistry Registry;
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RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
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: MachinePassRegistryNode(N, D, (MachinePassCtor)C)
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{ Registry.Add(this); }
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~RegisterScheduler() { Registry.Remove(this); }
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// Accessors.
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//
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RegisterScheduler *getNext() const {
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return (RegisterScheduler *)MachinePassRegistryNode::getNext();
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}
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static RegisterScheduler *getList() {
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return (RegisterScheduler *)Registry.getList();
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}
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static FunctionPassCtor getDefault() {
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return (FunctionPassCtor)Registry.getDefault();
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}
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static void setDefault(FunctionPassCtor C) {
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Registry.setDefault((MachinePassCtor)C);
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}
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static void setListener(MachinePassRegistryListener *L) {
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Registry.setListener(L);
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}
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};
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/// createBURRListDAGScheduler - This creates a bottom up register usage
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/// reduction list scheduler.
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ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level OptLevel);
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/// createBURRListDAGScheduler - This creates a bottom up list scheduler that
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/// schedules nodes in source code order when possible.
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ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level OptLevel);
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/// createHybridListDAGScheduler - This creates a bottom up register pressure
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/// aware list scheduler that make use of latency information to avoid stalls
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/// for long latency instructions in low register pressure mode. In high
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/// register pressure mode it schedules to reduce register pressure.
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ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level);
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/// createILPListDAGScheduler - This creates a bottom up register pressure
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/// aware list scheduler that tries to increase instruction level parallelism
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/// in low register pressure mode. In high register pressure mode it schedules
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/// to reduce register pressure.
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ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level);
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/// createFastDAGScheduler - This creates a "fast" scheduler.
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///
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ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level OptLevel);
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/// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down
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/// DFA driven list scheduler with clustering heuristic to control
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/// register pressure.
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ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level OptLevel);
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/// createDefaultScheduler - This creates an instruction scheduler appropriate
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/// for the target.
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ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level OptLevel);
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/// createDAGLinearizer - This creates a "no-scheduling" scheduler which
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/// linearize the DAG using topological order.
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ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS,
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CodeGenOpt::Level OptLevel);
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} // end namespace llvm
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#endif
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