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https://github.com/c64scene-ar/llvm-6502.git
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bbc726d624
regB = move RCX
regA = op regB, regC
RAX = move regA
where both regB and regC are killed. If regB is constrainted to non-compatible
physical registers but regC is not constrainted at all, then it's better to
commute the instruction.
movl %edi, %eax
shlq $32, %rcx
leaq (%rcx,%rax), %rax
=>
movl %edi, %eax
shlq $32, %rcx
orq %rcx, %rax
rdar://8762995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121793 91177308-0d34-0410-b5e6-96231b3b80d8
64 lines
1.8 KiB
LLVM
64 lines
1.8 KiB
LLVM
; The register allocator can commute two-address instructions to avoid
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; insertion of register-register copies.
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; Make sure there are only 3 mov's for each testcase
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; RUN: llc < %s -mtriple=i686-pc-linux-gnu | FileCheck %s -check-prefix=LINUX
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; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s -check-prefix=DARWIN
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@G = external global i32 ; <i32*> [#uses=2]
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declare void @ext(i32)
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define i32 @t1(i32 %X, i32 %Y) nounwind {
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; LINUX: t1:
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; LINUX: movl 4(%esp), %eax
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; LINUX: movl 8(%esp), %ecx
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; LINUX: addl %eax, %ecx
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; LINUX: movl %ecx, G
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%Z = add i32 %X, %Y ; <i32> [#uses=1]
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store i32 %Z, i32* @G
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ret i32 %X
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}
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define i32 @t2(i32 %X, i32 %Y) nounwind {
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; LINUX: t2:
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; LINUX: movl 4(%esp), %eax
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; LINUX: movl 8(%esp), %ecx
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; LINUX: xorl %eax, %ecx
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; LINUX: movl %ecx, G
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%Z = xor i32 %X, %Y ; <i32> [#uses=1]
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store i32 %Z, i32* @G
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ret i32 %X
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}
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; rdar://8762995
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%0 = type { i64, i32 }
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define %0 @t3(i32 %lb, i8 zeroext %has_lb, i8 zeroext %lb_inclusive, i32 %ub, i8 zeroext %has_ub, i8 zeroext %ub_inclusive) nounwind {
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entry:
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; DARWIN: t3:
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; DARWIN: shlq $32, %rcx
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; DARWIN-NOT: leaq
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; DARWIN: orq %rcx, %rax
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; DARWIN-NOT: mov
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; DARWIN: shll $16
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%tmp21 = zext i32 %lb to i64
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%tmp23 = zext i32 %ub to i64
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%tmp24 = shl i64 %tmp23, 32
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%ins26 = or i64 %tmp24, %tmp21
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%tmp28 = zext i8 %has_lb to i32
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%tmp33 = zext i8 %has_ub to i32
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%tmp34 = shl i32 %tmp33, 8
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%tmp38 = zext i8 %lb_inclusive to i32
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%tmp39 = shl i32 %tmp38, 16
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%tmp43 = zext i8 %ub_inclusive to i32
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%tmp44 = shl i32 %tmp43, 24
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%ins31 = or i32 %tmp39, %tmp28
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%ins36 = or i32 %ins31, %tmp34
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%ins46 = or i32 %ins36, %tmp44
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%tmp16 = insertvalue %0 undef, i64 %ins26, 0
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%tmp19 = insertvalue %0 %tmp16, i32 %ins46, 1
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ret %0 %tmp19
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}
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