mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81112 91177308-0d34-0410-b5e6-96231b3b80d8
1095 lines
40 KiB
C++
1095 lines
40 KiB
C++
//===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a top-down list scheduler, using standard algorithms.
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// The basic approach uses a priority queue of available nodes to schedule.
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// One at a time, nodes are taken from the priority queue (thus in priority
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// order), checked for legality to schedule, and emitted if legal.
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//
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// Nodes may not be legal to schedule either due to structural hazards (e.g.
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// pipeline or resource constraints) or because an input to the instruction has
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// not completed execution.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "post-RA-sched"
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#include "ExactHazardRecognizer.h"
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#include "SimpleHazardRecognizer.h"
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#include "ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/LatencyPriorityQueue.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/Statistic.h"
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#include <map>
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#include <set>
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using namespace llvm;
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STATISTIC(NumNoops, "Number of noops inserted");
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STATISTIC(NumStalls, "Number of pipeline stalls");
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static cl::opt<bool>
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EnableAntiDepBreaking("break-anti-dependencies",
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cl::desc("Break post-RA scheduling anti-dependencies"),
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cl::init(true), cl::Hidden);
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static cl::opt<bool>
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EnablePostRAHazardAvoidance("avoid-hazards",
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cl::desc("Enable exact hazard avoidance"),
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cl::init(true), cl::Hidden);
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// If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
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static cl::opt<int>
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DebugDiv("postra-sched-debugdiv",
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cl::desc("Debug control MBBs that are scheduled"),
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cl::init(0), cl::Hidden);
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static cl::opt<int>
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DebugMod("postra-sched-debugmod",
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cl::desc("Debug control MBBs that are scheduled"),
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cl::init(0), cl::Hidden);
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namespace {
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class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
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public:
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static char ID;
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PostRAScheduler() : MachineFunctionPass(&ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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const char *getPassName() const {
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return "Post RA top-down list latency scheduler";
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}
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bool runOnMachineFunction(MachineFunction &Fn);
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};
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char PostRAScheduler::ID = 0;
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class VISIBILITY_HIDDEN SchedulePostRATDList : public ScheduleDAGInstrs {
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/// AvailableQueue - The priority queue to use for the available SUnits.
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///
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LatencyPriorityQueue AvailableQueue;
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/// PendingQueue - This contains all of the instructions whose operands have
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/// been issued, but their results are not ready yet (due to the latency of
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/// the operation). Once the operands becomes available, the instruction is
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/// added to the AvailableQueue.
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std::vector<SUnit*> PendingQueue;
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/// Topo - A topological ordering for SUnits.
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ScheduleDAGTopologicalSort Topo;
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/// AllocatableSet - The set of allocatable registers.
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/// We'll be ignoring anti-dependencies on non-allocatable registers,
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/// because they may not be safe to break.
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const BitVector AllocatableSet;
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/// HazardRec - The hazard recognizer to use.
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ScheduleHazardRecognizer *HazardRec;
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/// Classes - For live regs that are only used in one register class in a
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/// live range, the register class. If the register is not live, the
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/// corresponding value is null. If the register is live but used in
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/// multiple register classes, the corresponding value is -1 casted to a
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/// pointer.
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const TargetRegisterClass *
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Classes[TargetRegisterInfo::FirstVirtualRegister];
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/// RegRegs - Map registers to all their references within a live range.
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std::multimap<unsigned, MachineOperand *> RegRefs;
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/// The index of the most recent kill (proceding bottom-up), or ~0u if
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/// the register is not live.
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unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
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/// The index of the most recent complete def (proceding bottom up), or ~0u
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/// if the register is live.
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unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
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public:
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SchedulePostRATDList(MachineFunction &MF,
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const MachineLoopInfo &MLI,
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const MachineDominatorTree &MDT,
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ScheduleHazardRecognizer *HR)
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: ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
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AllocatableSet(TRI->getAllocatableSet(MF)),
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HazardRec(HR) {}
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~SchedulePostRATDList() {
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delete HazardRec;
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}
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/// StartBlock - Initialize register live-range state for scheduling in
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/// this block.
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///
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void StartBlock(MachineBasicBlock *BB);
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/// Schedule - Schedule the instruction range using list scheduling.
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///
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void Schedule();
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/// FixupKills - Fix register kill flags that have been made
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/// invalid due to scheduling
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///
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void FixupKills(MachineBasicBlock *MBB);
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/// Observe - Update liveness information to account for the current
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/// instruction, which will not be scheduled.
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///
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void Observe(MachineInstr *MI, unsigned Count);
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/// FinishBlock - Clean up register live-range state.
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///
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void FinishBlock();
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private:
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void PrescanInstruction(MachineInstr *MI);
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void ScanInstruction(MachineInstr *MI, unsigned Count);
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void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
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void ReleaseSuccessors(SUnit *SU);
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void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
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void ListScheduleTopDown();
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bool BreakAntiDependencies();
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unsigned findSuitableFreeRegister(unsigned AntiDepReg,
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unsigned LastNewReg,
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const TargetRegisterClass *);
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void StartBlockForKills(MachineBasicBlock *BB);
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};
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}
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/// isSchedulingBoundary - Test if the given instruction should be
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/// considered a scheduling boundary. This primarily includes labels
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/// and terminators.
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///
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static bool isSchedulingBoundary(const MachineInstr *MI,
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const MachineFunction &MF) {
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// Terminators and labels can't be scheduled around.
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if (MI->getDesc().isTerminator() || MI->isLabel())
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return true;
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// Don't attempt to schedule around any instruction that modifies
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// a stack-oriented pointer, as it's unlikely to be profitable. This
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// saves compile time, because it doesn't require every single
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// stack slot reference to depend on the instruction that does the
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// modification.
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const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
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if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore()))
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return true;
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return false;
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}
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bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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DEBUG(errs() << "PostRAScheduler\n");
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const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
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const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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const InstrItineraryData &InstrItins = Fn.getTarget().getInstrItineraryData();
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ScheduleHazardRecognizer *HR = EnablePostRAHazardAvoidance ?
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(ScheduleHazardRecognizer *)new ExactHazardRecognizer(InstrItins) :
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(ScheduleHazardRecognizer *)new SimpleHazardRecognizer();
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SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR);
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// Loop over all of the basic blocks
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB) {
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#ifndef NDEBUG
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// If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
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if (DebugDiv > 0) {
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static int bbcnt = 0;
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if (bbcnt++ % DebugDiv != DebugMod)
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continue;
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errs() << "*** DEBUG scheduling " << Fn.getFunction()->getNameStr() <<
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":MBB ID#" << MBB->getNumber() << " ***\n";
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}
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#endif
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// Initialize register live-range state for scheduling in this block.
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Scheduler.StartBlock(MBB);
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// Schedule each sequence of instructions not interrupted by a label
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// or anything else that effectively needs to shut down scheduling.
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MachineBasicBlock::iterator Current = MBB->end();
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unsigned Count = MBB->size(), CurrentCount = Count;
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for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
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MachineInstr *MI = prior(I);
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if (isSchedulingBoundary(MI, Fn)) {
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Scheduler.Run(MBB, I, Current, CurrentCount);
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Scheduler.EmitSchedule();
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Current = MI;
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CurrentCount = Count - 1;
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Scheduler.Observe(MI, CurrentCount);
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}
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I = MI;
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--Count;
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}
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assert(Count == 0 && "Instruction count mismatch!");
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assert((MBB->begin() == Current || CurrentCount != 0) &&
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"Instruction count mismatch!");
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Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount);
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Scheduler.EmitSchedule();
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// Clean up register live-range state.
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Scheduler.FinishBlock();
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// Update register kills
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Scheduler.FixupKills(MBB);
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}
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return true;
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}
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/// StartBlock - Initialize register live-range state for scheduling in
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/// this block.
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///
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void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
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// Call the superclass.
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ScheduleDAGInstrs::StartBlock(BB);
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// Reset the hazard recognizer.
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HazardRec->Reset();
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// Clear out the register class data.
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std::fill(Classes, array_endof(Classes),
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static_cast<const TargetRegisterClass *>(0));
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// Initialize the indices to indicate that no registers are live.
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std::fill(KillIndices, array_endof(KillIndices), ~0u);
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std::fill(DefIndices, array_endof(DefIndices), BB->size());
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// Determine the live-out physregs for this block.
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if (!BB->empty() && BB->back().getDesc().isReturn())
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// In a return block, examine the function live-out regs.
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for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
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E = MRI.liveout_end(); I != E; ++I) {
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unsigned Reg = *I;
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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}
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}
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else
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// In a non-return block, examine the live-in regs of all successors.
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for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
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SE = BB->succ_end(); SI != SE; ++SI)
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for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
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E = (*SI)->livein_end(); I != E; ++I) {
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unsigned Reg = *I;
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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}
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}
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// Consider callee-saved registers as live-out, since we're running after
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// prologue/epilogue insertion so there's no way to add additional
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// saved registers.
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//
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// TODO: there is a new method
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// MachineFrameInfo::getPristineRegs(MBB). It gives you a list of
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// CSRs that have not been saved when entering the MBB. The
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// remaining CSRs have been saved and can be treated like call
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// clobbered registers.
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for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
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unsigned Reg = *I;
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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}
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}
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}
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/// Schedule - Schedule the instruction range using list scheduling.
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///
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void SchedulePostRATDList::Schedule() {
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DEBUG(errs() << "********** List Scheduling **********\n");
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// Build the scheduling graph.
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BuildSchedGraph();
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if (EnableAntiDepBreaking) {
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if (BreakAntiDependencies()) {
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// We made changes. Update the dependency graph.
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// Theoretically we could update the graph in place:
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// When a live range is changed to use a different register, remove
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// the def's anti-dependence *and* output-dependence edges due to
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// that register, and add new anti-dependence and output-dependence
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// edges based on the next live range of the register.
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SUnits.clear();
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EntrySU = SUnit();
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ExitSU = SUnit();
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BuildSchedGraph();
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}
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}
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(this));
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AvailableQueue.initNodes(SUnits);
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ListScheduleTopDown();
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AvailableQueue.releaseState();
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}
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/// Observe - Update liveness information to account for the current
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/// instruction, which will not be scheduled.
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///
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void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
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assert(Count < InsertPosIndex && "Instruction index out of expected range!");
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// Any register which was defined within the previous scheduling region
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// may have been rescheduled and its lifetime may overlap with registers
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// in ways not reflected in our current liveness state. For each such
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// register, adjust the liveness state to be conservatively correct.
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for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg)
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if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
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assert(KillIndices[Reg] == ~0u && "Clobbered register is live!");
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// Mark this register to be non-renamable.
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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// Move the def index to the end of the previous region, to reflect
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// that the def could theoretically have been scheduled at the end.
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DefIndices[Reg] = InsertPosIndex;
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}
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PrescanInstruction(MI);
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ScanInstruction(MI, Count);
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}
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/// FinishBlock - Clean up register live-range state.
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///
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void SchedulePostRATDList::FinishBlock() {
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RegRefs.clear();
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// Call the superclass.
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ScheduleDAGInstrs::FinishBlock();
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}
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/// CriticalPathStep - Return the next SUnit after SU on the bottom-up
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/// critical path.
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static SDep *CriticalPathStep(SUnit *SU) {
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SDep *Next = 0;
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unsigned NextDepth = 0;
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// Find the predecessor edge with the greatest depth.
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for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
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P != PE; ++P) {
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SUnit *PredSU = P->getSUnit();
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unsigned PredLatency = P->getLatency();
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unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
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// In the case of a latency tie, prefer an anti-dependency edge over
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// other types of edges.
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if (NextDepth < PredTotalLatency ||
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(NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
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NextDepth = PredTotalLatency;
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Next = &*P;
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}
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}
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return Next;
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}
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void SchedulePostRATDList::PrescanInstruction(MachineInstr *MI) {
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// Scan the register operands for this instruction and update
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// Classes and RegRefs.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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const TargetRegisterClass *NewRC = 0;
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if (i < MI->getDesc().getNumOperands())
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NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
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// For now, only allow the register to be changed if its register
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// class is consistent across all uses.
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if (!Classes[Reg] && NewRC)
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Classes[Reg] = NewRC;
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else if (!NewRC || Classes[Reg] != NewRC)
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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// Now check for aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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// If an alias of the reg is used during the live range, give up.
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// Note that this allows us to skip checking if AntiDepReg
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// overlaps with any of the aliases, among other things.
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unsigned AliasReg = *Alias;
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if (Classes[AliasReg]) {
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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}
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}
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// If we're still willing to consider this register, note the reference.
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if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
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RegRefs.insert(std::make_pair(Reg, &MO));
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}
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}
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void SchedulePostRATDList::ScanInstruction(MachineInstr *MI,
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unsigned Count) {
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// Update liveness.
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// Proceding upwards, registers that are defed but not used in this
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// instruction are now dead.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
if (!MO.isDef()) continue;
|
|
// Ignore two-addr defs.
|
|
if (MI->isRegTiedToUseOperand(i)) continue;
|
|
|
|
DefIndices[Reg] = Count;
|
|
KillIndices[Reg] = ~0u;
|
|
assert(((KillIndices[Reg] == ~0u) !=
|
|
(DefIndices[Reg] == ~0u)) &&
|
|
"Kill and Def maps aren't consistent for Reg!");
|
|
Classes[Reg] = 0;
|
|
RegRefs.erase(Reg);
|
|
// Repeat, for all subregs.
|
|
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
|
|
*Subreg; ++Subreg) {
|
|
unsigned SubregReg = *Subreg;
|
|
DefIndices[SubregReg] = Count;
|
|
KillIndices[SubregReg] = ~0u;
|
|
Classes[SubregReg] = 0;
|
|
RegRefs.erase(SubregReg);
|
|
}
|
|
// Conservatively mark super-registers as unusable.
|
|
for (const unsigned *Super = TRI->getSuperRegisters(Reg);
|
|
*Super; ++Super) {
|
|
unsigned SuperReg = *Super;
|
|
Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);
|
|
}
|
|
}
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
if (!MO.isUse()) continue;
|
|
|
|
const TargetRegisterClass *NewRC = 0;
|
|
if (i < MI->getDesc().getNumOperands())
|
|
NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
|
|
|
|
// For now, only allow the register to be changed if its register
|
|
// class is consistent across all uses.
|
|
if (!Classes[Reg] && NewRC)
|
|
Classes[Reg] = NewRC;
|
|
else if (!NewRC || Classes[Reg] != NewRC)
|
|
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
|
|
|
|
RegRefs.insert(std::make_pair(Reg, &MO));
|
|
|
|
// It wasn't previously live but now it is, this is a kill.
|
|
if (KillIndices[Reg] == ~0u) {
|
|
KillIndices[Reg] = Count;
|
|
DefIndices[Reg] = ~0u;
|
|
assert(((KillIndices[Reg] == ~0u) !=
|
|
(DefIndices[Reg] == ~0u)) &&
|
|
"Kill and Def maps aren't consistent for Reg!");
|
|
}
|
|
// Repeat, for all aliases.
|
|
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
|
|
unsigned AliasReg = *Alias;
|
|
if (KillIndices[AliasReg] == ~0u) {
|
|
KillIndices[AliasReg] = Count;
|
|
DefIndices[AliasReg] = ~0u;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned
|
|
SchedulePostRATDList::findSuitableFreeRegister(unsigned AntiDepReg,
|
|
unsigned LastNewReg,
|
|
const TargetRegisterClass *RC) {
|
|
for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF),
|
|
RE = RC->allocation_order_end(MF); R != RE; ++R) {
|
|
unsigned NewReg = *R;
|
|
// Don't replace a register with itself.
|
|
if (NewReg == AntiDepReg) continue;
|
|
// Don't replace a register with one that was recently used to repair
|
|
// an anti-dependence with this AntiDepReg, because that would
|
|
// re-introduce that anti-dependence.
|
|
if (NewReg == LastNewReg) continue;
|
|
// If NewReg is dead and NewReg's most recent def is not before
|
|
// AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
|
|
assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) &&
|
|
"Kill and Def maps aren't consistent for AntiDepReg!");
|
|
assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) &&
|
|
"Kill and Def maps aren't consistent for NewReg!");
|
|
if (KillIndices[NewReg] != ~0u ||
|
|
Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
|
|
KillIndices[AntiDepReg] > DefIndices[NewReg])
|
|
continue;
|
|
return NewReg;
|
|
}
|
|
|
|
// No registers are free and available!
|
|
return 0;
|
|
}
|
|
|
|
/// BreakAntiDependencies - Identifiy anti-dependencies along the critical path
|
|
/// of the ScheduleDAG and break them by renaming registers.
|
|
///
|
|
bool SchedulePostRATDList::BreakAntiDependencies() {
|
|
// The code below assumes that there is at least one instruction,
|
|
// so just duck out immediately if the block is empty.
|
|
if (SUnits.empty()) return false;
|
|
|
|
// Find the node at the bottom of the critical path.
|
|
SUnit *Max = 0;
|
|
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
|
SUnit *SU = &SUnits[i];
|
|
if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
|
|
Max = SU;
|
|
}
|
|
|
|
DEBUG(errs() << "Critical path has total latency "
|
|
<< (Max->getDepth() + Max->Latency) << "\n");
|
|
|
|
// Track progress along the critical path through the SUnit graph as we walk
|
|
// the instructions.
|
|
SUnit *CriticalPathSU = Max;
|
|
MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
|
|
|
|
// Consider this pattern:
|
|
// A = ...
|
|
// ... = A
|
|
// A = ...
|
|
// ... = A
|
|
// A = ...
|
|
// ... = A
|
|
// A = ...
|
|
// ... = A
|
|
// There are three anti-dependencies here, and without special care,
|
|
// we'd break all of them using the same register:
|
|
// A = ...
|
|
// ... = A
|
|
// B = ...
|
|
// ... = B
|
|
// B = ...
|
|
// ... = B
|
|
// B = ...
|
|
// ... = B
|
|
// because at each anti-dependence, B is the first register that
|
|
// isn't A which is free. This re-introduces anti-dependencies
|
|
// at all but one of the original anti-dependencies that we were
|
|
// trying to break. To avoid this, keep track of the most recent
|
|
// register that each register was replaced with, avoid
|
|
// using it to repair an anti-dependence on the same register.
|
|
// This lets us produce this:
|
|
// A = ...
|
|
// ... = A
|
|
// B = ...
|
|
// ... = B
|
|
// C = ...
|
|
// ... = C
|
|
// B = ...
|
|
// ... = B
|
|
// This still has an anti-dependence on B, but at least it isn't on the
|
|
// original critical path.
|
|
//
|
|
// TODO: If we tracked more than one register here, we could potentially
|
|
// fix that remaining critical edge too. This is a little more involved,
|
|
// because unlike the most recent register, less recent registers should
|
|
// still be considered, though only if no other registers are available.
|
|
unsigned LastNewReg[TargetRegisterInfo::FirstVirtualRegister] = {};
|
|
|
|
// Attempt to break anti-dependence edges on the critical path. Walk the
|
|
// instructions from the bottom up, tracking information about liveness
|
|
// as we go to help determine which registers are available.
|
|
bool Changed = false;
|
|
unsigned Count = InsertPosIndex - 1;
|
|
for (MachineBasicBlock::iterator I = InsertPos, E = Begin;
|
|
I != E; --Count) {
|
|
MachineInstr *MI = --I;
|
|
|
|
// After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
|
|
// dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF
|
|
// is left behind appearing to clobber the super-register, while the
|
|
// subregister needs to remain live. So we just ignore them.
|
|
if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
|
|
continue;
|
|
|
|
// Check if this instruction has a dependence on the critical path that
|
|
// is an anti-dependence that we may be able to break. If it is, set
|
|
// AntiDepReg to the non-zero register associated with the anti-dependence.
|
|
//
|
|
// We limit our attention to the critical path as a heuristic to avoid
|
|
// breaking anti-dependence edges that aren't going to significantly
|
|
// impact the overall schedule. There are a limited number of registers
|
|
// and we want to save them for the important edges.
|
|
//
|
|
// TODO: Instructions with multiple defs could have multiple
|
|
// anti-dependencies. The current code here only knows how to break one
|
|
// edge per instruction. Note that we'd have to be able to break all of
|
|
// the anti-dependencies in an instruction in order to be effective.
|
|
unsigned AntiDepReg = 0;
|
|
if (MI == CriticalPathMI) {
|
|
if (SDep *Edge = CriticalPathStep(CriticalPathSU)) {
|
|
SUnit *NextSU = Edge->getSUnit();
|
|
|
|
// Only consider anti-dependence edges.
|
|
if (Edge->getKind() == SDep::Anti) {
|
|
AntiDepReg = Edge->getReg();
|
|
assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
|
|
// Don't break anti-dependencies on non-allocatable registers.
|
|
if (!AllocatableSet.test(AntiDepReg))
|
|
AntiDepReg = 0;
|
|
else {
|
|
// If the SUnit has other dependencies on the SUnit that it
|
|
// anti-depends on, don't bother breaking the anti-dependency
|
|
// since those edges would prevent such units from being
|
|
// scheduled past each other regardless.
|
|
//
|
|
// Also, if there are dependencies on other SUnits with the
|
|
// same register as the anti-dependency, don't attempt to
|
|
// break it.
|
|
for (SUnit::pred_iterator P = CriticalPathSU->Preds.begin(),
|
|
PE = CriticalPathSU->Preds.end(); P != PE; ++P)
|
|
if (P->getSUnit() == NextSU ?
|
|
(P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
|
|
(P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
|
|
AntiDepReg = 0;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
CriticalPathSU = NextSU;
|
|
CriticalPathMI = CriticalPathSU->getInstr();
|
|
} else {
|
|
// We've reached the end of the critical path.
|
|
CriticalPathSU = 0;
|
|
CriticalPathMI = 0;
|
|
}
|
|
}
|
|
|
|
PrescanInstruction(MI);
|
|
|
|
// If this instruction has a use of AntiDepReg, breaking it
|
|
// is invalid.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
if (MO.isUse() && AntiDepReg == Reg) {
|
|
AntiDepReg = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Determine AntiDepReg's register class, if it is live and is
|
|
// consistently used within a single class.
|
|
const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0;
|
|
assert((AntiDepReg == 0 || RC != NULL) &&
|
|
"Register should be live if it's causing an anti-dependence!");
|
|
if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
|
|
AntiDepReg = 0;
|
|
|
|
// Look for a suitable register to use to break the anti-depenence.
|
|
//
|
|
// TODO: Instead of picking the first free register, consider which might
|
|
// be the best.
|
|
if (AntiDepReg != 0) {
|
|
if (unsigned NewReg = findSuitableFreeRegister(AntiDepReg,
|
|
LastNewReg[AntiDepReg],
|
|
RC)) {
|
|
DEBUG(errs() << "Breaking anti-dependence edge on "
|
|
<< TRI->getName(AntiDepReg)
|
|
<< " with " << RegRefs.count(AntiDepReg) << " references"
|
|
<< " using " << TRI->getName(NewReg) << "!\n");
|
|
|
|
// Update the references to the old register to refer to the new
|
|
// register.
|
|
std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
|
|
std::multimap<unsigned, MachineOperand *>::iterator>
|
|
Range = RegRefs.equal_range(AntiDepReg);
|
|
for (std::multimap<unsigned, MachineOperand *>::iterator
|
|
Q = Range.first, QE = Range.second; Q != QE; ++Q)
|
|
Q->second->setReg(NewReg);
|
|
|
|
// We just went back in time and modified history; the
|
|
// liveness information for the anti-depenence reg is now
|
|
// inconsistent. Set the state as if it were dead.
|
|
Classes[NewReg] = Classes[AntiDepReg];
|
|
DefIndices[NewReg] = DefIndices[AntiDepReg];
|
|
KillIndices[NewReg] = KillIndices[AntiDepReg];
|
|
assert(((KillIndices[NewReg] == ~0u) !=
|
|
(DefIndices[NewReg] == ~0u)) &&
|
|
"Kill and Def maps aren't consistent for NewReg!");
|
|
|
|
Classes[AntiDepReg] = 0;
|
|
DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
|
|
KillIndices[AntiDepReg] = ~0u;
|
|
assert(((KillIndices[AntiDepReg] == ~0u) !=
|
|
(DefIndices[AntiDepReg] == ~0u)) &&
|
|
"Kill and Def maps aren't consistent for AntiDepReg!");
|
|
|
|
RegRefs.erase(AntiDepReg);
|
|
Changed = true;
|
|
LastNewReg[AntiDepReg] = NewReg;
|
|
}
|
|
}
|
|
|
|
ScanInstruction(MI, Count);
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
/// StartBlockForKills - Initialize register live-range state for updating kills
|
|
///
|
|
void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) {
|
|
// Initialize the indices to indicate that no registers are live.
|
|
std::fill(KillIndices, array_endof(KillIndices), ~0u);
|
|
|
|
// Determine the live-out physregs for this block.
|
|
if (!BB->empty() && BB->back().getDesc().isReturn()) {
|
|
// In a return block, examine the function live-out regs.
|
|
for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
|
|
E = MRI.liveout_end(); I != E; ++I) {
|
|
unsigned Reg = *I;
|
|
KillIndices[Reg] = BB->size();
|
|
// Repeat, for all subregs.
|
|
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
|
|
*Subreg; ++Subreg) {
|
|
KillIndices[*Subreg] = BB->size();
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
// In a non-return block, examine the live-in regs of all successors.
|
|
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
|
|
SE = BB->succ_end(); SI != SE; ++SI) {
|
|
for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
|
|
E = (*SI)->livein_end(); I != E; ++I) {
|
|
unsigned Reg = *I;
|
|
KillIndices[Reg] = BB->size();
|
|
// Repeat, for all subregs.
|
|
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
|
|
*Subreg; ++Subreg) {
|
|
KillIndices[*Subreg] = BB->size();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// FixupKills - Fix the register kill flags, they may have been made
|
|
/// incorrect by instruction reordering.
|
|
///
|
|
void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
|
|
DEBUG(errs() << "Fixup kills for BB ID#" << MBB->getNumber() << '\n');
|
|
|
|
std::set<unsigned> killedRegs;
|
|
BitVector ReservedRegs = TRI->getReservedRegs(MF);
|
|
|
|
StartBlockForKills(MBB);
|
|
|
|
// Examine block from end to start...
|
|
unsigned Count = MBB->size();
|
|
for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
|
|
I != E; --Count) {
|
|
MachineInstr *MI = --I;
|
|
|
|
// Update liveness. Registers that are defed but not used in this
|
|
// instruction are now dead. Mark register and all subregs as they
|
|
// are completely defined.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
if (!MO.isDef()) continue;
|
|
// Ignore two-addr defs.
|
|
if (MI->isRegTiedToUseOperand(i)) continue;
|
|
|
|
KillIndices[Reg] = ~0u;
|
|
|
|
// Repeat for all subregs.
|
|
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
|
|
*Subreg; ++Subreg) {
|
|
KillIndices[*Subreg] = ~0u;
|
|
}
|
|
}
|
|
|
|
// Examine all used registers and set kill flag. When a register
|
|
// is used multiple times we only set the kill flag on the first
|
|
// use.
|
|
killedRegs.clear();
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || !MO.isUse()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
|
|
|
|
bool kill = false;
|
|
if (killedRegs.find(Reg) == killedRegs.end()) {
|
|
kill = true;
|
|
// A register is not killed if any subregs are live...
|
|
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
|
|
*Subreg; ++Subreg) {
|
|
if (KillIndices[*Subreg] != ~0u) {
|
|
kill = false;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// If subreg is not live, then register is killed if it became
|
|
// live in this instruction
|
|
if (kill)
|
|
kill = (KillIndices[Reg] == ~0u);
|
|
}
|
|
|
|
if (MO.isKill() != kill) {
|
|
MO.setIsKill(kill);
|
|
DEBUG(errs() << "Fixed " << MO << " in ");
|
|
DEBUG(MI->dump());
|
|
}
|
|
|
|
killedRegs.insert(Reg);
|
|
}
|
|
|
|
// Mark any used register (that is not using undef) and subregs as
|
|
// now live...
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
|
|
|
|
KillIndices[Reg] = Count;
|
|
|
|
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
|
|
*Subreg; ++Subreg) {
|
|
KillIndices[*Subreg] = Count;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Top-Down Scheduling
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
|
|
/// the PendingQueue if the count reaches zero. Also update its cycle bound.
|
|
void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
|
|
SUnit *SuccSU = SuccEdge->getSUnit();
|
|
--SuccSU->NumPredsLeft;
|
|
|
|
#ifndef NDEBUG
|
|
if (SuccSU->NumPredsLeft < 0) {
|
|
errs() << "*** Scheduling failed! ***\n";
|
|
SuccSU->dump(this);
|
|
errs() << " has been released too many times!\n";
|
|
llvm_unreachable(0);
|
|
}
|
|
#endif
|
|
|
|
// Compute how many cycles it will be before this actually becomes
|
|
// available. This is the max of the start time of all predecessors plus
|
|
// their latencies.
|
|
SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
|
|
|
|
// If all the node's predecessors are scheduled, this node is ready
|
|
// to be scheduled. Ignore the special ExitSU node.
|
|
if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
|
|
PendingQueue.push_back(SuccSU);
|
|
}
|
|
|
|
/// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
|
|
void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I)
|
|
ReleaseSucc(SU, &*I);
|
|
}
|
|
|
|
/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
|
|
/// count of its successors. If a successor pending count is zero, add it to
|
|
/// the Available queue.
|
|
void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
|
|
DEBUG(errs() << "*** Scheduling [" << CurCycle << "]: ");
|
|
DEBUG(SU->dump(this));
|
|
|
|
Sequence.push_back(SU);
|
|
assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
|
|
SU->setDepthToAtLeast(CurCycle);
|
|
|
|
ReleaseSuccessors(SU);
|
|
SU->isScheduled = true;
|
|
AvailableQueue.ScheduledNode(SU);
|
|
}
|
|
|
|
/// ListScheduleTopDown - The main loop of list scheduling for top-down
|
|
/// schedulers.
|
|
void SchedulePostRATDList::ListScheduleTopDown() {
|
|
unsigned CurCycle = 0;
|
|
|
|
// Release any successors of the special Entry node.
|
|
ReleaseSuccessors(&EntrySU);
|
|
|
|
// All leaves to Available queue.
|
|
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
|
// It is available if it has no predecessors.
|
|
if (SUnits[i].Preds.empty()) {
|
|
AvailableQueue.push(&SUnits[i]);
|
|
SUnits[i].isAvailable = true;
|
|
}
|
|
}
|
|
|
|
// In any cycle where we can't schedule any instructions, we must
|
|
// stall or emit a noop, depending on the target.
|
|
bool CycleHasInsts = false;
|
|
|
|
// While Available queue is not empty, grab the node with the highest
|
|
// priority. If it is not ready put it back. Schedule the node.
|
|
std::vector<SUnit*> NotReady;
|
|
Sequence.reserve(SUnits.size());
|
|
while (!AvailableQueue.empty() || !PendingQueue.empty()) {
|
|
// Check to see if any of the pending instructions are ready to issue. If
|
|
// so, add them to the available queue.
|
|
unsigned MinDepth = ~0u;
|
|
for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
|
|
if (PendingQueue[i]->getDepth() <= CurCycle) {
|
|
AvailableQueue.push(PendingQueue[i]);
|
|
PendingQueue[i]->isAvailable = true;
|
|
PendingQueue[i] = PendingQueue.back();
|
|
PendingQueue.pop_back();
|
|
--i; --e;
|
|
} else if (PendingQueue[i]->getDepth() < MinDepth)
|
|
MinDepth = PendingQueue[i]->getDepth();
|
|
}
|
|
|
|
DEBUG(errs() << "\n*** Examining Available\n";
|
|
LatencyPriorityQueue q = AvailableQueue;
|
|
while (!q.empty()) {
|
|
SUnit *su = q.pop();
|
|
errs() << "Height " << su->getHeight() << ": ";
|
|
su->dump(this);
|
|
});
|
|
|
|
SUnit *FoundSUnit = 0;
|
|
|
|
bool HasNoopHazards = false;
|
|
while (!AvailableQueue.empty()) {
|
|
SUnit *CurSUnit = AvailableQueue.pop();
|
|
|
|
ScheduleHazardRecognizer::HazardType HT =
|
|
HazardRec->getHazardType(CurSUnit);
|
|
if (HT == ScheduleHazardRecognizer::NoHazard) {
|
|
FoundSUnit = CurSUnit;
|
|
break;
|
|
}
|
|
|
|
// Remember if this is a noop hazard.
|
|
HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
|
|
|
|
NotReady.push_back(CurSUnit);
|
|
}
|
|
|
|
// Add the nodes that aren't ready back onto the available list.
|
|
if (!NotReady.empty()) {
|
|
AvailableQueue.push_all(NotReady);
|
|
NotReady.clear();
|
|
}
|
|
|
|
// If we found a node to schedule, do it now.
|
|
if (FoundSUnit) {
|
|
ScheduleNodeTopDown(FoundSUnit, CurCycle);
|
|
HazardRec->EmitInstruction(FoundSUnit);
|
|
CycleHasInsts = true;
|
|
|
|
// If we are using the target-specific hazards, then don't
|
|
// advance the cycle time just because we schedule a node. If
|
|
// the target allows it we can schedule multiple nodes in the
|
|
// same cycle.
|
|
if (!EnablePostRAHazardAvoidance) {
|
|
if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
|
|
++CurCycle;
|
|
}
|
|
} else {
|
|
if (CycleHasInsts) {
|
|
DEBUG(errs() << "*** Finished cycle " << CurCycle << '\n');
|
|
HazardRec->AdvanceCycle();
|
|
} else if (!HasNoopHazards) {
|
|
// Otherwise, we have a pipeline stall, but no other problem,
|
|
// just advance the current cycle and try again.
|
|
DEBUG(errs() << "*** Stall in cycle " << CurCycle << '\n');
|
|
HazardRec->AdvanceCycle();
|
|
++NumStalls;
|
|
} else {
|
|
// Otherwise, we have no instructions to issue and we have instructions
|
|
// that will fault if we don't do this right. This is the case for
|
|
// processors without pipeline interlocks and other cases.
|
|
DEBUG(errs() << "*** Emitting noop in cycle " << CurCycle << '\n');
|
|
HazardRec->EmitNoop();
|
|
Sequence.push_back(0); // NULL here means noop
|
|
++NumNoops;
|
|
}
|
|
|
|
++CurCycle;
|
|
CycleHasInsts = false;
|
|
}
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
VerifySchedule(/*isBottomUp=*/false);
|
|
#endif
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Public Constructor Functions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
FunctionPass *llvm::createPostRAScheduler() {
|
|
return new PostRAScheduler();
|
|
}
|