mirror of
https://github.com/c64scene-ar/llvm-6502.git
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be49526193
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1185 91177308-0d34-0410-b5e6-96231b3b80d8
290 lines
9.3 KiB
C++
290 lines
9.3 KiB
C++
// $Id$ -*-c++-*-
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//***************************************************************************
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// File:
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// InstrSelection.cpp
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//
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// Purpose:
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// Machine-independent driver file for instruction selection.
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// This file constructs a forest of BURG instruction trees and then
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// uses the BURG-generated tree grammar (BURM) to find the optimal
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// instruction sequences for a given machine.
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//
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// History:
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// 7/02/01 - Vikram Adve - Created
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//**************************************************************************/
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/InstrSelectionSupport.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Instruction.h"
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#include "llvm/BasicBlock.h"
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#include "llvm/Method.h"
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//******************** Internal Data Declarations ************************/
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// Use a static vector to avoid allocating a new one per VM instruction
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static MachineInstr* minstrVec[MAX_INSTR_PER_VMINSTR];
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enum SelectDebugLevel_t {
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Select_NoDebugInfo,
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Select_PrintMachineCode,
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Select_DebugInstTrees,
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Select_DebugBurgTrees,
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};
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// Enable Debug Options to be specified on the command line
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cl::Enum<enum SelectDebugLevel_t> SelectDebugLevel("dselect", cl::NoFlags,
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"enable instruction selection debugging information",
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clEnumValN(Select_NoDebugInfo, "n", "disable debug output"),
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clEnumValN(Select_PrintMachineCode, "y", "print generated machine code"),
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clEnumValN(Select_DebugInstTrees, "i", "print debugging info for instruction selection "),
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clEnumValN(Select_DebugBurgTrees, "b", "print burg trees"), 0);
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//******************** Forward Function Declarations ***********************/
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static bool SelectInstructionsForTree (InstrTreeNode* treeRoot,
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int goalnt,
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TargetMachine &target);
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static void PostprocessMachineCodeForTree(InstructionNode* instrNode,
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int ruleForNode,
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short* nts,
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TargetMachine &target);
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//******************* Externally Visible Functions *************************/
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//---------------------------------------------------------------------------
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// Entry point for instruction selection using BURG.
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// Returns true if instruction selection failed, false otherwise.
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//---------------------------------------------------------------------------
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bool
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SelectInstructionsForMethod(Method* method, TargetMachine &target)
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{
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bool failed = false;
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//
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// Build the instruction trees to be given as inputs to BURG.
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//
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InstrForest instrForest(method);
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if (SelectDebugLevel >= Select_DebugInstTrees)
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{
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cout << "\n\n*** Instruction trees for method "
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<< (method->hasName()? method->getName() : "")
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<< endl << endl;
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instrForest.dump();
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}
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//
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// Invoke BURG instruction selection for each tree
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//
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const hash_set<InstructionNode*> &treeRoots = instrForest.getRootSet();
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for (hash_set<InstructionNode*>::const_iterator
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treeRootIter = treeRoots.begin(); treeRootIter != treeRoots.end();
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++treeRootIter)
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{
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InstrTreeNode* basicNode = *treeRootIter;
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// Invoke BURM to label each tree node with a state
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burm_label(basicNode);
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if (SelectDebugLevel >= Select_DebugBurgTrees)
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{
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printcover(basicNode, 1, 0);
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cerr << "\nCover cost == " << treecost(basicNode, 1, 0) << "\n\n";
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printMatches(basicNode);
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}
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// Then recursively walk the tree to select instructions
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if (SelectInstructionsForTree(basicNode, /*goalnt*/1, target))
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{
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failed = true;
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break;
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}
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}
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//
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// Record instructions in the vector for each basic block
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//
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for (Method::iterator BI = method->begin(); BI != method->end(); ++BI)
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{
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MachineCodeForBasicBlock& bbMvec = (*BI)->getMachineInstrVec();
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for (BasicBlock::iterator II = (*BI)->begin(); II != (*BI)->end(); ++II)
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{
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MachineCodeForVMInstr& mvec = (*II)->getMachineInstrVec();
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for (unsigned i=0; i < mvec.size(); i++)
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bbMvec.push_back(mvec[i]);
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}
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}
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if (SelectDebugLevel >= Select_PrintMachineCode)
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{
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cout << endl
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<< "*** Machine instructions after INSTRUCTION SELECTION" << endl;
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MachineCodeForMethod::get(method).dump();
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}
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return false;
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}
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//*********************** Private Functions *****************************/
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//---------------------------------------------------------------------------
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// Function AppendMachineCodeForVMInstr
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//
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// Append machine instr sequence to the machine code vec for a VM instr
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//---------------------------------------------------------------------------
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inline void
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AppendMachineCodeForVMInstr(MachineInstr** minstrVec,
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unsigned int N,
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Instruction* vmInstr)
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{
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if (N == 0)
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return;
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MachineCodeForVMInstr& mvec = vmInstr->getMachineInstrVec();
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mvec.insert(mvec.end(), minstrVec, minstrVec+N);
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}
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//---------------------------------------------------------------------------
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// Function PostprocessMachineCodeForTree
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//
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// Apply any final cleanups to machine code for the root of a subtree
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// after selection for all its children has been completed.
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//---------------------------------------------------------------------------
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static void
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PostprocessMachineCodeForTree(InstructionNode* instrNode,
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int ruleForNode,
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short* nts,
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TargetMachine &target)
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{
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// Fix up any constant operands in the machine instructions to either
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// use an immediate field or to load the constant into a register
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// Walk backwards and use direct indexes to allow insertion before current
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//
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Instruction* vmInstr = instrNode->getInstruction();
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MachineCodeForVMInstr& mvec = vmInstr->getMachineInstrVec();
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for (int i = (int) mvec.size()-1; i >= 0; i--)
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{
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vector<MachineInstr*> loadConstVec =
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FixConstantOperandsForInstr(vmInstr, mvec[i], target);
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if (loadConstVec.size() > 0)
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mvec.insert(mvec.begin()+i, loadConstVec.begin(), loadConstVec.end());
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}
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}
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//---------------------------------------------------------------------------
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// Function SelectInstructionsForTree
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//
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// Recursively walk the tree to select instructions.
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// Do this top-down so that child instructions can exploit decisions
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// made at the child instructions.
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//
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// E.g., if br(setle(reg,const)) decides the constant is 0 and uses
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// a branch-on-integer-register instruction, then the setle node
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// can use that information to avoid generating the SUBcc instruction.
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//
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// Note that this cannot be done bottom-up because setle must do this
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// only if it is a child of the branch (otherwise, the result of setle
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// may be used by multiple instructions).
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//---------------------------------------------------------------------------
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bool
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SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt,
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TargetMachine &target)
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{
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// Get the rule that matches this node.
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//
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int ruleForNode = burm_rule(treeRoot->state, goalnt);
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if (ruleForNode == 0)
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{
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cerr << "Could not match instruction tree for instr selection" << endl;
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assert(0);
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return true;
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}
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// Get this rule's non-terminals and the corresponding child nodes (if any)
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//
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short *nts = burm_nts[ruleForNode];
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// First, select instructions for the current node and rule.
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// (If this is a list node, not an instruction, then skip this step).
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// This function is specific to the target architecture.
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//
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if (treeRoot->opLabel != VRegListOp)
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{
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InstructionNode* instrNode = (InstructionNode*)treeRoot;
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assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);
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unsigned N = GetInstructionsByRule(instrNode, ruleForNode, nts, target,
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minstrVec);
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if (N > 0)
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{
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assert(N <= MAX_INSTR_PER_VMINSTR);
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AppendMachineCodeForVMInstr(minstrVec,N,instrNode->getInstruction());
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}
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}
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// Then, recursively compile the child nodes, if any.
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//
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if (nts[0])
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{ // i.e., there is at least one kid
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InstrTreeNode* kids[2];
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int currentRule = ruleForNode;
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burm_kids(treeRoot, currentRule, kids);
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// First skip over any chain rules so that we don't visit
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// the current node again.
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//
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while (ThisIsAChainRule(currentRule))
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{
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currentRule = burm_rule(treeRoot->state, nts[0]);
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nts = burm_nts[currentRule];
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burm_kids(treeRoot, currentRule, kids);
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}
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// Now we have the first non-chain rule so we have found
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// the actual child nodes. Recursively compile them.
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//
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for (int i = 0; nts[i]; i++)
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{
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assert(i < 2);
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InstrTreeNode::InstrTreeNodeType nodeType = kids[i]->getNodeType();
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if (nodeType == InstrTreeNode::NTVRegListNode ||
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nodeType == InstrTreeNode::NTInstructionNode)
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{
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if (SelectInstructionsForTree(kids[i], nts[i], target))
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return true; // failure
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}
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}
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}
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// Finally, do any postprocessing on this node after its children
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// have been translated
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//
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if (treeRoot->opLabel != VRegListOp)
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{
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InstructionNode* instrNode = (InstructionNode*)treeRoot;
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PostprocessMachineCodeForTree(instrNode, ruleForNode, nts, target);
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}
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return false; // success
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}
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