mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a0792de66c
allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
93 lines
2.4 KiB
LLVM
93 lines
2.4 KiB
LLVM
; RUN: llc < %s -march=arm | FileCheck %s
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; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s --check-prefix=CHECK-VFP
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; RUN: llc < %s -mattr=+neon,+thumb2 -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=CHECK-NEON
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define i32 @f1(i32 %a.s) {
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;CHECK: f1:
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;CHECK: moveq
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entry:
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%tmp = icmp eq i32 %a.s, 4
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f2(i32 %a.s) {
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;CHECK: f2:
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;CHECK: movgt
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entry:
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%tmp = icmp sgt i32 %a.s, 4
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f3(i32 %a.s, i32 %b.s) {
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;CHECK: f3:
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;CHECK: movlt
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entry:
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%tmp = icmp slt i32 %a.s, %b.s
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f4(i32 %a.s, i32 %b.s) {
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;CHECK: f4:
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;CHECK: movle
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entry:
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%tmp = icmp sle i32 %a.s, %b.s
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f5(i32 %a.u, i32 %b.u) {
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;CHECK: f5:
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;CHECK: movls
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entry:
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%tmp = icmp ule i32 %a.u, %b.u
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f6(i32 %a.u, i32 %b.u) {
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;CHECK: f6:
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;CHECK: movhi
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entry:
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%tmp = icmp ugt i32 %a.u, %b.u
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define double @f7(double %a, double %b) {
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;CHECK: f7:
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;CHECK: movlt
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;CHECK: movlt
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;CHECK-VFP: f7:
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;CHECK-VFP: vmovmi
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%tmp = fcmp olt double %a, 1.234e+00
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%tmp1 = select i1 %tmp, double -1.000e+00, double %b
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ret double %tmp1
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}
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; <rdar://problem/7260094>
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;
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; We used to generate really horrible code for this function. The main cause was
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; a lack of a custom lowering routine for an ISD::SELECT. This would result in
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; two "it" blocks in the code: one for the "icmp" and another to move the index
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; into the constant pool based on the value of the "icmp". If we have one "it"
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; block generated, odds are good that we have close to the ideal code for this:
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;
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; CHECK-NEON: _f8:
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; CHECK-NEON: movw [[REGISTER_1:r[0-9]+]], #1123
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; CHECK-NEON-NEXT: movs [[REGISTER_2:r[0-9]+]], #0
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; CHECK-NEON-NEXT: cmp r0, [[REGISTER_1]]
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; CHECK-NEON-NEXT: it eq
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; CHECK-NEON-NEXT: moveq [[REGISTER_2]], #4
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; CHECK-NEON-NEXT: adr [[REGISTER_3:r[0-9]+]], #LCPI
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; CHECK-NEON-NEXT: ldr
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; CHECK-NEON: bx
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define arm_apcscc float @f8(i32 %a) nounwind {
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%tmp = icmp eq i32 %a, 1123
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%tmp1 = select i1 %tmp, float 0x3FF3BE76C0000000, float 0x40030E9A20000000
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ret float %tmp1
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}
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