mirror of
https://github.com/c64scene-ar/llvm-6502.git
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beb07e117d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26302 91177308-0d34-0410-b5e6-96231b3b80d8
401 lines
20 KiB
C++
401 lines
20 KiB
C++
//====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the Evan Cheng and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 SSE instruction set, defining the instructions,
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// and properties of the instructions which are needed for code generation,
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// machine code emission, and analysis.
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//
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//===----------------------------------------------------------------------===//
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def MOVAPSrr : I<0x28, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
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"movaps {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, TB;
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def MOVAPDrr : I<0x28, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
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"movapd {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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def MOVAPSrm : I<0x28, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
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"movaps {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, TB;
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def MOVAPSmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V4F32:$src),
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"movaps {$src, $dst|$dst, $src}",[]>,
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Requires<[HasSSE1]>, TB;
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def MOVAPDrm : I<0x28, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
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"movapd {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, TB, OpSize;
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def MOVAPDmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V2F64:$src),
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"movapd {$src, $dst|$dst, $src}",[]>,
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Requires<[HasSSE2]>, TB, OpSize;
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// Logical
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let isTwoAddress = 1 in {
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let isCommutable = 1 in {
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def ANDPSrr : I<0x54, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
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"andps {$src2, $dst|$dst, $src2}",
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[(set V4F32:$dst, (X86fand V4F32:$src1, V4F32:$src2))]>,
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Requires<[HasSSE1]>, TB;
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def ANDPDrr : I<0x54, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
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"andpd {$src2, $dst|$dst, $src2}",
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[(set V2F64:$dst, (X86fand V2F64:$src1, V2F64:$src2))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def ORPSrr : I<0x56, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
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"orps {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE1]>, TB;
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def ORPDrr : I<0x56, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
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"orpd {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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def XORPSrr : I<0x57, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
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"xorps {$src2, $dst|$dst, $src2}",
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[(set V4F32:$dst, (X86fxor V4F32:$src1, V4F32:$src2))]>,
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Requires<[HasSSE1]>, TB;
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def XORPDrr : I<0x57, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
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"xorpd {$src2, $dst|$dst, $src2}",
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[(set V2F64:$dst, (X86fxor V2F64:$src1, V2F64:$src2))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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}
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def ANDPSrm : I<0x54, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
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"andps {$src2, $dst|$dst, $src2}",
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[(set V4F32:$dst, (X86fand V4F32:$src1,
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(X86loadpv4f32 addr:$src2)))]>,
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Requires<[HasSSE1]>, TB;
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def ANDPDrm : I<0x54, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
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"andpd {$src2, $dst|$dst, $src2}",
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[(set V2F64:$dst, (X86fand V2F64:$src1,
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(X86loadpv2f64 addr:$src2)))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def ORPSrm : I<0x56, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
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"orps {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE1]>, TB;
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def ORPDrm : I<0x56, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
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"orpd {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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def XORPSrm : I<0x57, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
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"xorps {$src2, $dst|$dst, $src2}",
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[(set V4F32:$dst, (X86fxor V4F32:$src1,
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(X86loadpv4f32 addr:$src2)))]>,
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Requires<[HasSSE1]>, TB;
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def XORPDrm : I<0x57, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
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"xorpd {$src2, $dst|$dst, $src2}",
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[(set V2F64:$dst, (X86fxor V2F64:$src1,
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(X86loadpv2f64 addr:$src2)))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def ANDNPSrr : I<0x55, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
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"andnps {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE1]>, TB;
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def ANDNPSrm : I<0x55, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
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"andnps {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE1]>, TB;
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def ANDNPDrr : I<0x55, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
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"andnpd {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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def ANDNPDrm : I<0x55, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
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"andnpd {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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}
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def MOVSSrr : I<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
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"movss {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, XS;
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def MOVSDrr : I<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
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"movsd {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE2]>, XD;
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def MOVSSrm : I<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
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"movss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (loadf32 addr:$src))]>,
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Requires<[HasSSE1]>, XS;
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def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
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"movss {$src, $dst|$dst, $src}",
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[(store FR32:$src, addr:$dst)]>,
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Requires<[HasSSE1]>, XS;
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def MOVSDrm : I<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
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"movsd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (loadf64 addr:$src))]>,
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Requires<[HasSSE2]>, XD;
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def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
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"movsd {$src, $dst|$dst, $src}",
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[(store FR64:$src, addr:$dst)]>,
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Requires<[HasSSE2]>, XD;
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def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
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"cvttss2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (fp_to_sint FR32:$src))]>,
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Requires<[HasSSE1]>, XS;
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def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
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"cvttss2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>,
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Requires<[HasSSE1]>, XS;
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def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
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"cvttsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (fp_to_sint FR64:$src))]>,
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Requires<[HasSSE2]>, XD;
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def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
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"cvttsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>,
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Requires<[HasSSE2]>, XD;
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def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
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"cvtss2sd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fextend FR32:$src))]>,
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Requires<[HasSSE2]>, XS;
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def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
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"cvtss2sd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fextend (loadf32 addr:$src)))]>,
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Requires<[HasSSE2]>, XS;
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def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
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"cvtsd2ss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround FR64:$src))]>,
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Requires<[HasSSE2]>, XD;
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def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
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"cvtsd2ss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround (loadf64 addr:$src)))]>,
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Requires<[HasSSE2]>, XD;
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def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
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"cvtsi2ss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (sint_to_fp R32:$src))]>,
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Requires<[HasSSE2]>, XS;
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def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
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"cvtsi2ss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>,
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Requires<[HasSSE2]>, XS;
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def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
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"cvtsi2sd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (sint_to_fp R32:$src))]>,
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Requires<[HasSSE2]>, XD;
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def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
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"cvtsi2sd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>,
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Requires<[HasSSE2]>, XD;
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def SQRTSSrr : I<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
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"sqrtss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fsqrt FR32:$src))]>,
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Requires<[HasSSE1]>, XS;
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def SQRTSSrm : I<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
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"sqrtss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>,
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Requires<[HasSSE1]>, XS;
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def SQRTSDrr : I<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
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"sqrtsd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fsqrt FR64:$src))]>,
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Requires<[HasSSE2]>, XD;
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def SQRTSDrm : I<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
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"sqrtsd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>,
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Requires<[HasSSE2]>, XD;
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def UCOMISSrr: I<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
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"ucomiss {$src2, $src1|$src1, $src2}",
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[(X86cmp FR32:$src1, FR32:$src2)]>,
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Requires<[HasSSE1]>, TB;
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def UCOMISSrm: I<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
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"ucomiss {$src2, $src1|$src1, $src2}",
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[(X86cmp FR32:$src1, (loadf32 addr:$src2))]>,
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Requires<[HasSSE1]>, TB;
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def UCOMISDrr: I<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
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"ucomisd {$src2, $src1|$src1, $src2}",
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[(X86cmp FR64:$src1, FR64:$src2)]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def UCOMISDrm: I<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
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"ucomisd {$src2, $src1|$src1, $src2}",
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[(X86cmp FR64:$src1, (loadf64 addr:$src2))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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let isTwoAddress = 1 in {
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// SSE Scalar Arithmetic
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let isCommutable = 1 in {
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def ADDSSrr : I<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
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"addss {$src2, $dst|$dst, $src2}",
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[(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>,
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Requires<[HasSSE1]>, XS;
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def ADDSDrr : I<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
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"addsd {$src2, $dst|$dst, $src2}",
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[(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>,
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Requires<[HasSSE2]>, XD;
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def MULSSrr : I<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
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"mulss {$src2, $dst|$dst, $src2}",
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[(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>,
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Requires<[HasSSE1]>, XS;
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def MULSDrr : I<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
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"mulsd {$src2, $dst|$dst, $src2}",
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[(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>,
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Requires<[HasSSE2]>, XD;
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}
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def ADDSSrm : I<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
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"addss {$src2, $dst|$dst, $src2}",
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[(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>,
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Requires<[HasSSE1]>, XS;
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def ADDSDrm : I<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
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"addsd {$src2, $dst|$dst, $src2}",
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[(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>,
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Requires<[HasSSE2]>, XD;
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def MULSSrm : I<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
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"mulss {$src2, $dst|$dst, $src2}",
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[(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>,
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Requires<[HasSSE1]>, XS;
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def MULSDrm : I<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
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"mulsd {$src2, $dst|$dst, $src2}",
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[(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>,
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Requires<[HasSSE2]>, XD;
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def DIVSSrr : I<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
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"divss {$src2, $dst|$dst, $src2}",
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[(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>,
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Requires<[HasSSE1]>, XS;
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def DIVSSrm : I<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
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"divss {$src2, $dst|$dst, $src2}",
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[(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>,
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Requires<[HasSSE1]>, XS;
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def DIVSDrr : I<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
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"divsd {$src2, $dst|$dst, $src2}",
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[(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>,
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Requires<[HasSSE2]>, XD;
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def DIVSDrm : I<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
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"divsd {$src2, $dst|$dst, $src2}",
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[(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>,
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Requires<[HasSSE2]>, XD;
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def SUBSSrr : I<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
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"subss {$src2, $dst|$dst, $src2}",
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[(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>,
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Requires<[HasSSE1]>, XS;
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def SUBSSrm : I<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
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"subss {$src2, $dst|$dst, $src2}",
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[(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>,
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Requires<[HasSSE1]>, XS;
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def SUBSDrr : I<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
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"subsd {$src2, $dst|$dst, $src2}",
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[(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>,
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Requires<[HasSSE2]>, XD;
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def SUBSDrm : I<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
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"subsd {$src2, $dst|$dst, $src2}",
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[(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>,
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Requires<[HasSSE2]>, XD;
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// SSE compare
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def CMPSSrr : I<0xC2, MRMSrcReg,
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(ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
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"cmp${cc}ss {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, XS;
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def CMPSSrm : I<0xC2, MRMSrcMem,
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(ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
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"cmp${cc}ss {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, XS;
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def CMPSDrr : I<0xC2, MRMSrcReg,
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(ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
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"cmp${cc}sd {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, XD;
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def CMPSDrm : I<0xC2, MRMSrcMem,
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(ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
|
|
"cmp${cc}sd {$src, $dst|$dst, $src}", []>,
|
|
Requires<[HasSSE2]>, XD;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Alias Instructions
|
|
//===----------------------------------------------------------------------===//
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|
|
|
// Alias instructions that map fld0 to pxor for sse.
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// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
|
|
def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
|
|
"pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
|
|
Requires<[HasSSE1]>, TB, OpSize;
|
|
def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
|
|
"pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
|
|
Requires<[HasSSE2]>, TB, OpSize;
|
|
|
|
// Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
|
|
// Upper bits are disregarded.
|
|
def FsMOVAPSrr : I<0x28, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
|
|
"movaps {$src, $dst|$dst, $src}", []>,
|
|
Requires<[HasSSE1]>, TB;
|
|
def FsMOVAPDrr : I<0x28, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
|
|
"movapd {$src, $dst|$dst, $src}", []>,
|
|
Requires<[HasSSE2]>, TB, OpSize;
|
|
|
|
// Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
|
|
// Upper bits are disregarded.
|
|
def FsMOVAPSrm : I<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
|
|
"movaps {$src, $dst|$dst, $src}",
|
|
[(set FR32:$dst, (X86loadpf32 addr:$src))]>,
|
|
Requires<[HasSSE1]>, TB;
|
|
def FsMOVAPDrm : I<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
|
|
"movapd {$src, $dst|$dst, $src}",
|
|
[(set FR64:$dst, (X86loadpf64 addr:$src))]>,
|
|
Requires<[HasSSE2]>, TB, OpSize;
|
|
|
|
// Alias bitwise logical operations using SSE logical ops on packed FP values.
|
|
let isTwoAddress = 1 in {
|
|
let isCommutable = 1 in {
|
|
def FsANDPSrr : I<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
|
|
"andps {$src2, $dst|$dst, $src2}",
|
|
[(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>,
|
|
Requires<[HasSSE1]>, TB;
|
|
def FsANDPDrr : I<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
|
|
"andpd {$src2, $dst|$dst, $src2}",
|
|
[(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>,
|
|
Requires<[HasSSE2]>, TB, OpSize;
|
|
def FsORPSrr : I<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
|
|
"orps {$src2, $dst|$dst, $src2}", []>,
|
|
Requires<[HasSSE1]>, TB;
|
|
def FsORPDrr : I<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
|
|
"orpd {$src2, $dst|$dst, $src2}", []>,
|
|
Requires<[HasSSE2]>, TB, OpSize;
|
|
def FsXORPSrr : I<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
|
|
"xorps {$src2, $dst|$dst, $src2}",
|
|
[(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>,
|
|
Requires<[HasSSE1]>, TB;
|
|
def FsXORPDrr : I<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
|
|
"xorpd {$src2, $dst|$dst, $src2}",
|
|
[(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>,
|
|
Requires<[HasSSE2]>, TB, OpSize;
|
|
}
|
|
def FsANDPSrm : I<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
|
|
"andps {$src2, $dst|$dst, $src2}",
|
|
[(set FR32:$dst, (X86fand FR32:$src1,
|
|
(X86loadpf32 addr:$src2)))]>,
|
|
Requires<[HasSSE1]>, TB;
|
|
def FsANDPDrm : I<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
|
|
"andpd {$src2, $dst|$dst, $src2}",
|
|
[(set FR64:$dst, (X86fand FR64:$src1,
|
|
(X86loadpf64 addr:$src2)))]>,
|
|
Requires<[HasSSE2]>, TB, OpSize;
|
|
def FsORPSrm : I<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
|
|
"orps {$src2, $dst|$dst, $src2}", []>,
|
|
Requires<[HasSSE1]>, TB;
|
|
def FsORPDrm : I<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
|
|
"orpd {$src2, $dst|$dst, $src2}", []>,
|
|
Requires<[HasSSE2]>, TB, OpSize;
|
|
def FsXORPSrm : I<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
|
|
"xorps {$src2, $dst|$dst, $src2}",
|
|
[(set FR32:$dst, (X86fxor FR32:$src1,
|
|
(X86loadpf32 addr:$src2)))]>,
|
|
Requires<[HasSSE1]>, TB;
|
|
def FsXORPDrm : I<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
|
|
"xorpd {$src2, $dst|$dst, $src2}",
|
|
[(set FR64:$dst, (X86fxor FR64:$src1,
|
|
(X86loadpf64 addr:$src2)))]>,
|
|
Requires<[HasSSE2]>, TB, OpSize;
|
|
|
|
def FsANDNPSrr : I<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
|
|
"andnps {$src2, $dst|$dst, $src2}", []>,
|
|
Requires<[HasSSE1]>, TB;
|
|
def FsANDNPSrm : I<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
|
|
"andnps {$src2, $dst|$dst, $src2}", []>,
|
|
Requires<[HasSSE1]>, TB;
|
|
def FsANDNPDrr : I<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
|
|
"andnpd {$src2, $dst|$dst, $src2}", []>,
|
|
Requires<[HasSSE2]>, TB, OpSize;
|
|
def FsANDNPDrm : I<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
|
|
"andnpd {$src2, $dst|$dst, $src2}", []>,
|
|
Requires<[HasSSE2]>, TB, OpSize;
|
|
}
|