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https://github.com/c64scene-ar/llvm-6502.git
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e45ab8a0a9
function can support dynamic stack realignment. That's a much easier question to answer at instruction selection stage than whether the function actually will have dynamic alignment prologue. This allows the removal of the stack alignment heuristic pass, and improves code quality for cases where the heuristic would result in dynamic alignment code being generated when it was not strictly necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93885 91177308-0d34-0410-b5e6-96231b3b80d8
278 lines
10 KiB
C++
278 lines
10 KiB
C++
//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "X86MCAsmInfo.h"
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#include "X86TargetMachine.h"
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#include "X86.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegistry.h"
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using namespace llvm;
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static const MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
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Triple TheTriple(TT);
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switch (TheTriple.getOS()) {
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case Triple::Darwin:
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return new X86MCAsmInfoDarwin(TheTriple);
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case Triple::MinGW32:
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case Triple::MinGW64:
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case Triple::Cygwin:
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return new X86MCAsmInfoCOFF(TheTriple);
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case Triple::Win32:
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return new X86WinMCAsmInfo(TheTriple);
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default:
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return new X86ELFMCAsmInfo(TheTriple);
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}
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}
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extern "C" void LLVMInitializeX86Target() {
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// Register the target.
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RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
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RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
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// Register the target asm info.
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RegisterAsmInfoFn A(TheX86_32Target, createMCAsmInfo);
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RegisterAsmInfoFn B(TheX86_64Target, createMCAsmInfo);
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// Register the code emitter.
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TargetRegistry::RegisterCodeEmitter(TheX86_32Target, createX86MCCodeEmitter);
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TargetRegistry::RegisterCodeEmitter(TheX86_64Target, createX86MCCodeEmitter);
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}
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X86_32TargetMachine::X86_32TargetMachine(const Target &T, const std::string &TT,
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const std::string &FS)
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: X86TargetMachine(T, TT, FS, false) {
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}
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X86_64TargetMachine::X86_64TargetMachine(const Target &T, const std::string &TT,
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const std::string &FS)
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: X86TargetMachine(T, TT, FS, true) {
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}
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/// X86TargetMachine ctor - Create an X86 target.
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///
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X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
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const std::string &FS, bool is64Bit)
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: LLVMTargetMachine(T, TT),
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Subtarget(TT, FS, is64Bit),
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DataLayout(Subtarget.getDataLayout()),
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FrameInfo(TargetFrameInfo::StackGrowsDown,
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Subtarget.getStackAlignment(),
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(Subtarget.isTargetWin64() ? -40 :
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(Subtarget.is64Bit() ? -8 : -4))),
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InstrInfo(*this), JITInfo(*this), TLInfo(*this), ELFWriterInfo(*this) {
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DefRelocModel = getRelocationModel();
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// If no relocation model was picked, default as appropriate for the target.
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if (getRelocationModel() == Reloc::Default) {
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if (!Subtarget.isTargetDarwin())
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setRelocationModel(Reloc::Static);
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else if (Subtarget.is64Bit())
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setRelocationModel(Reloc::PIC_);
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else
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setRelocationModel(Reloc::DynamicNoPIC);
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}
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assert(getRelocationModel() != Reloc::Default &&
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"Relocation mode not picked");
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// ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
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// is defined as a model for code which may be used in static or dynamic
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// executables but not necessarily a shared library. On X86-32 we just
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// compile in -static mode, in x86-64 we use PIC.
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if (getRelocationModel() == Reloc::DynamicNoPIC) {
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if (is64Bit)
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setRelocationModel(Reloc::PIC_);
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else if (!Subtarget.isTargetDarwin())
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setRelocationModel(Reloc::Static);
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}
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// If we are on Darwin, disallow static relocation model in X86-64 mode, since
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// the Mach-O file format doesn't support it.
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if (getRelocationModel() == Reloc::Static &&
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Subtarget.isTargetDarwin() &&
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is64Bit)
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setRelocationModel(Reloc::PIC_);
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// Determine the PICStyle based on the target selected.
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if (getRelocationModel() == Reloc::Static) {
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// Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
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Subtarget.setPICStyle(PICStyles::None);
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} else if (Subtarget.isTargetCygMing()) {
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Subtarget.setPICStyle(PICStyles::None);
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} else if (Subtarget.isTargetDarwin()) {
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if (Subtarget.is64Bit())
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Subtarget.setPICStyle(PICStyles::RIPRel);
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else if (getRelocationModel() == Reloc::PIC_)
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Subtarget.setPICStyle(PICStyles::StubPIC);
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else {
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assert(getRelocationModel() == Reloc::DynamicNoPIC);
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Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
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}
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} else if (Subtarget.isTargetELF()) {
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if (Subtarget.is64Bit())
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Subtarget.setPICStyle(PICStyles::RIPRel);
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else
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Subtarget.setPICStyle(PICStyles::GOT);
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}
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// Finally, if we have "none" as our PIC style, force to static mode.
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if (Subtarget.getPICStyle() == PICStyles::None)
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setRelocationModel(Reloc::Static);
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// Install an instruction selector.
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PM.add(createX86ISelDag(*this, OptLevel));
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// If we're using Fast-ISel, clean up the mess.
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if (EnableFastISel)
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PM.add(createDeadMachineInstructionElimPass());
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// Install a pass to insert x87 FP_REG_KILL instructions, as needed.
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PM.add(createX87FPRegKillInserterPass());
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return false;
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}
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bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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return false; // -print-machineinstr shouldn't print after this.
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}
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bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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PM.add(createX86FloatingPointStackifierPass());
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return true; // -print-machineinstr should print after this.
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}
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bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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MachineCodeEmitter &MCE) {
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// FIXME: Move this to TargetJITInfo!
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// On Darwin, do not override 64-bit setting made in X86TargetMachine().
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if (DefRelocModel == Reloc::Default &&
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(!Subtarget.isTargetDarwin() || !Subtarget.is64Bit())) {
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setRelocationModel(Reloc::Static);
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Subtarget.setPICStyle(PICStyles::None);
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}
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PM.add(createX86CodeEmitterPass(*this, MCE));
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return false;
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}
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bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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JITCodeEmitter &JCE) {
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// FIXME: Move this to TargetJITInfo!
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// On Darwin, do not override 64-bit setting made in X86TargetMachine().
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if (DefRelocModel == Reloc::Default &&
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(!Subtarget.isTargetDarwin() || !Subtarget.is64Bit())) {
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setRelocationModel(Reloc::Static);
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Subtarget.setPICStyle(PICStyles::None);
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}
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PM.add(createX86JITCodeEmitterPass(*this, JCE));
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return false;
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}
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bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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ObjectCodeEmitter &OCE) {
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PM.add(createX86ObjectCodeEmitterPass(*this, OCE));
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return false;
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}
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bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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MachineCodeEmitter &MCE) {
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PM.add(createX86CodeEmitterPass(*this, MCE));
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return false;
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}
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bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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JITCodeEmitter &JCE) {
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PM.add(createX86JITCodeEmitterPass(*this, JCE));
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return false;
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}
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bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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ObjectCodeEmitter &OCE) {
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PM.add(createX86ObjectCodeEmitterPass(*this, OCE));
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return false;
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}
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void X86TargetMachine::setCodeModelForStatic() {
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if (getCodeModel() != CodeModel::Default) return;
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// For static codegen, if we're not already set, use Small codegen.
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setCodeModel(CodeModel::Small);
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}
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void X86TargetMachine::setCodeModelForJIT() {
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if (getCodeModel() != CodeModel::Default) return;
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// 64-bit JIT places everything in the same buffer except external functions.
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if (Subtarget.is64Bit())
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setCodeModel(CodeModel::Large);
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else
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setCodeModel(CodeModel::Small);
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}
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/// getLSDAEncoding - Returns the LSDA pointer encoding. The choices are 4-byte,
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/// 8-byte, and target default. The CIE is hard-coded to indicate that the LSDA
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/// pointer in the FDE section is an "sdata4", and should be encoded as a 4-byte
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/// pointer by default. However, some systems may require a different size due
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/// to bugs or other conditions. We will default to a 4-byte encoding unless the
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/// system tells us otherwise.
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///
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/// The issue is when the CIE says their is an LSDA. That mandates that every
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/// FDE have an LSDA slot. But if the function does not need an LSDA. There
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/// needs to be some way to signify there is none. The LSDA is encoded as
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/// pc-rel. But you don't look for some magic value after adding the pc. You
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/// have to look for a zero before adding the pc. The problem is that the size
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/// of the zero to look for depends on the encoding. The unwinder bug in SL is
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/// that it always checks for a pointer-size zero. So on x86_64 it looks for 8
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/// bytes of zero. If you have an LSDA, it works fine since the 8-bytes are
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/// non-zero so it goes ahead and then reads the value based on the encoding.
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/// But if you use sdata4 and there is no LSDA, then the test for zero gives a
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/// false negative and the unwinder thinks there is an LSDA.
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///
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/// FIXME: This call-back isn't good! We should be using the correct encoding
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/// regardless of the system. However, there are some systems which have bugs
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/// that prevent this from occuring.
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DwarfLSDAEncoding::Encoding X86TargetMachine::getLSDAEncoding() const {
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if (Subtarget.isTargetDarwin() && Subtarget.getDarwinVers() != 10)
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return DwarfLSDAEncoding::Default;
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return DwarfLSDAEncoding::EightByte;
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}
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