llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00

History

Ahmed Bougacha bed2308186 Add a way to define the bit range covered by a SubRegIndex. NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8	2013-05-31 17:08:36 +00:00
..
llvm	Add a way to define the bit range covered by a SubRegIndex.	2013-05-31 17:08:36 +00:00
llvm-c	Add a new function attribute 'cold' to functions.	2013-05-24 12:26:52 +00:00

Ahmed Bougacha bed2308186 Add a way to define the bit range covered by a SubRegIndex.

NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change
the instances of SubRegIndex that have a comps template arg to use the
ComposedSubRegIndex class instead.

In TableGen land, this adds Size and Offset attributes to SubRegIndex,
and the ComposedSubRegIndex class, for which the Size and Offset are
computed by TableGen. This also adds an accessor in MCRegisterInfo, and
Size/Offsets for the X86 and ARM subreg indices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8

2013-05-31 17:08:36 +00:00

llvm

Add a way to define the bit range covered by a SubRegIndex.

2013-05-31 17:08:36 +00:00

llvm-c

Add a new function attribute 'cold' to functions.

2013-05-24 12:26:52 +00:00