mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233427 91177308-0d34-0410-b5e6-96231b3b80d8
1007 lines
37 KiB
C++
1007 lines
37 KiB
C++
//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SelectionDAG::LegalizeVectors method.
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//
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// The vector legalizer looks for vector operations which might need to be
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// scalarized and legalizes them. This is a separate step from Legalize because
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// scalarizing can introduce illegal types. For example, suppose we have an
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// ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
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// on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
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// operation, which introduces nodes with the illegal type i64 which must be
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// expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
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// the operation must be unrolled, which introduces nodes with the illegal
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// type i8 which must be promoted.
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//
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// This does not legalize vector manipulations like ISD::BUILD_VECTOR,
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// or operations that happen to take a vector which are custom-lowered;
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// the legalization for such operations never produces nodes
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// with illegal types, so it's okay to put off legalizing them until
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// SelectionDAG::Legalize runs.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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namespace {
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class VectorLegalizer {
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SelectionDAG& DAG;
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const TargetLowering &TLI;
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bool Changed; // Keep track of whether anything changed
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/// For nodes that are of legal width, and that have more than one use, this
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/// map indicates what regularized operand to use. This allows us to avoid
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/// legalizing the same thing more than once.
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SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
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/// \brief Adds a node to the translation cache.
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void AddLegalizedOperand(SDValue From, SDValue To) {
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LegalizedNodes.insert(std::make_pair(From, To));
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// If someone requests legalization of the new node, return itself.
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if (From != To)
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LegalizedNodes.insert(std::make_pair(To, To));
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}
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/// \brief Legalizes the given node.
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SDValue LegalizeOp(SDValue Op);
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/// \brief Assuming the node is legal, "legalize" the results.
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SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
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/// \brief Implements unrolling a VSETCC.
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SDValue UnrollVSETCC(SDValue Op);
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/// \brief Implement expand-based legalization of vector operations.
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///
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/// This is just a high-level routine to dispatch to specific code paths for
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/// operations to legalize them.
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SDValue Expand(SDValue Op);
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/// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
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/// FSUB isn't legal.
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///
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/// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
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/// SINT_TO_FLOAT and SHR on vectors isn't legal.
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SDValue ExpandUINT_TO_FLOAT(SDValue Op);
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/// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
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SDValue ExpandSEXTINREG(SDValue Op);
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/// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
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///
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/// Shuffles the low lanes of the operand into place and bitcasts to the proper
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/// type. The contents of the bits in the extended part of each element are
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/// undef.
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SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
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/// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
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///
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/// Shuffles the low lanes of the operand into place, bitcasts to the proper
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/// type, then shifts left and arithmetic shifts right to introduce a sign
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/// extension.
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SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
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/// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
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///
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/// Shuffles the low lanes of the operand into place and blends zeros into
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/// the remaining lanes, finally bitcasting to the proper type.
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SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
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/// \brief Expand bswap of vectors into a shuffle if legal.
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SDValue ExpandBSWAP(SDValue Op);
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/// \brief Implement vselect in terms of XOR, AND, OR when blend is not
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/// supported by the target.
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SDValue ExpandVSELECT(SDValue Op);
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SDValue ExpandSELECT(SDValue Op);
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SDValue ExpandLoad(SDValue Op);
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SDValue ExpandStore(SDValue Op);
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SDValue ExpandFNEG(SDValue Op);
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/// \brief Implements vector promotion.
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///
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/// This is essentially just bitcasting the operands to a different type and
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/// bitcasting the result back to the original type.
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SDValue Promote(SDValue Op);
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/// \brief Implements [SU]INT_TO_FP vector promotion.
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///
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/// This is a [zs]ext of the input operand to the next size up.
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SDValue PromoteINT_TO_FP(SDValue Op);
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/// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
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///
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/// It is promoted to the next size up integer type. The result is then
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/// truncated back to the original type.
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SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
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public:
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/// \brief Begin legalizer the vector operations in the DAG.
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bool Run();
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VectorLegalizer(SelectionDAG& dag) :
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DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
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};
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bool VectorLegalizer::Run() {
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// Before we start legalizing vector nodes, check if there are any vectors.
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bool HasVectors = false;
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for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
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E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
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// Check if the values of the nodes contain vectors. We don't need to check
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// the operands because we are going to check their values at some point.
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for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
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J != E; ++J)
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HasVectors |= J->isVector();
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// If we found a vector node we can start the legalization.
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if (HasVectors)
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break;
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}
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// If this basic block has no vectors then no need to legalize vectors.
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if (!HasVectors)
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return false;
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// The legalize process is inherently a bottom-up recursive process (users
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// legalize their uses before themselves). Given infinite stack space, we
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// could just start legalizing on the root and traverse the whole graph. In
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// practice however, this causes us to run out of stack space on large basic
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// blocks. To avoid this problem, compute an ordering of the nodes where each
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// node is only legalized after all of its operands are legalized.
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DAG.AssignTopologicalOrder();
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for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
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E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
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LegalizeOp(SDValue(I, 0));
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// Finally, it's possible the root changed. Get the new root.
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SDValue OldRoot = DAG.getRoot();
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assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
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DAG.setRoot(LegalizedNodes[OldRoot]);
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LegalizedNodes.clear();
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// Remove dead nodes now.
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DAG.RemoveDeadNodes();
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return Changed;
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}
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SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
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// Generic legalization: just pass the operand through.
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for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
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AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
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return Result.getValue(Op.getResNo());
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}
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SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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// Note that LegalizeOp may be reentered even from single-use nodes, which
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// means that we always must cache transformed nodes.
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DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
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if (I != LegalizedNodes.end()) return I->second;
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SDNode* Node = Op.getNode();
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// Legalize the operands
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SmallVector<SDValue, 8> Ops;
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for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
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Ops.push_back(LegalizeOp(Node->getOperand(i)));
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SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
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if (Op.getOpcode() == ISD::LOAD) {
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LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
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switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
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LD->getMemoryVT())) {
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default: llvm_unreachable("This action is not supported yet!");
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case TargetLowering::Legal:
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return TranslateLegalizeResults(Op, Result);
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case TargetLowering::Custom:
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if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
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if (Lowered == Result)
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return TranslateLegalizeResults(Op, Lowered);
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Changed = true;
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if (Lowered->getNumValues() != Op->getNumValues()) {
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// This expanded to something other than the load. Assume the
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// lowering code took care of any chain values, and just handle the
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// returned value.
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assert(Result.getValue(1).use_empty() &&
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"There are still live users of the old chain!");
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return LegalizeOp(Lowered);
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} else {
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return TranslateLegalizeResults(Op, Lowered);
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}
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}
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case TargetLowering::Expand:
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Changed = true;
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return LegalizeOp(ExpandLoad(Op));
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}
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} else if (Op.getOpcode() == ISD::STORE) {
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StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
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EVT StVT = ST->getMemoryVT();
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MVT ValVT = ST->getValue().getSimpleValueType();
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if (StVT.isVector() && ST->isTruncatingStore())
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switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
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default: llvm_unreachable("This action is not supported yet!");
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case TargetLowering::Legal:
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return TranslateLegalizeResults(Op, Result);
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case TargetLowering::Custom: {
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SDValue Lowered = TLI.LowerOperation(Result, DAG);
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Changed = Lowered != Result;
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return TranslateLegalizeResults(Op, Lowered);
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}
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case TargetLowering::Expand:
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Changed = true;
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return LegalizeOp(ExpandStore(Op));
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}
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}
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bool HasVectorValue = false;
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for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
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J != E;
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++J)
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HasVectorValue |= J->isVector();
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if (!HasVectorValue)
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return TranslateLegalizeResults(Op, Result);
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EVT QueryType;
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switch (Op.getOpcode()) {
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default:
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return TranslateLegalizeResults(Op, Result);
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case ISD::ADD:
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case ISD::SUB:
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case ISD::MUL:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::SREM:
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case ISD::UREM:
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::FDIV:
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case ISD::FREM:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRL:
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case ISD::ROTL:
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case ISD::ROTR:
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case ISD::BSWAP:
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case ISD::CTLZ:
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case ISD::CTTZ:
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case ISD::CTLZ_ZERO_UNDEF:
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case ISD::CTTZ_ZERO_UNDEF:
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case ISD::CTPOP:
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case ISD::SELECT:
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case ISD::VSELECT:
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case ISD::SELECT_CC:
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case ISD::SETCC:
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case ISD::ZERO_EXTEND:
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case ISD::ANY_EXTEND:
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case ISD::TRUNCATE:
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case ISD::SIGN_EXTEND:
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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case ISD::FNEG:
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case ISD::FABS:
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case ISD::FMINNUM:
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case ISD::FMAXNUM:
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case ISD::FCOPYSIGN:
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FPOWI:
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case ISD::FPOW:
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case ISD::FLOG:
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FEXP:
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case ISD::FEXP2:
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case ISD::FCEIL:
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case ISD::FTRUNC:
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case ISD::FRINT:
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case ISD::FNEARBYINT:
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case ISD::FROUND:
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case ISD::FFLOOR:
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case ISD::FP_ROUND:
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case ISD::FP_EXTEND:
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case ISD::FMA:
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case ISD::SIGN_EXTEND_INREG:
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case ISD::ANY_EXTEND_VECTOR_INREG:
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case ISD::SIGN_EXTEND_VECTOR_INREG:
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case ISD::ZERO_EXTEND_VECTOR_INREG:
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QueryType = Node->getValueType(0);
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break;
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case ISD::FP_ROUND_INREG:
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QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
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break;
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP:
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QueryType = Node->getOperand(0).getValueType();
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break;
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}
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switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
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case TargetLowering::Promote:
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Result = Promote(Op);
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Changed = true;
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break;
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case TargetLowering::Legal:
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break;
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case TargetLowering::Custom: {
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SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
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if (Tmp1.getNode()) {
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Result = Tmp1;
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break;
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}
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// FALL THROUGH
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}
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case TargetLowering::Expand:
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Result = Expand(Op);
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}
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// Make sure that the generated code is itself legal.
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if (Result != Op) {
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Result = LegalizeOp(Result);
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Changed = true;
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}
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// Note that LegalizeOp may be reentered even from single-use nodes, which
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// means that we always must cache transformed nodes.
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AddLegalizedOperand(Op, Result);
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return Result;
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}
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SDValue VectorLegalizer::Promote(SDValue Op) {
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// For a few operations there is a specific concept for promotion based on
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// the operand's type.
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switch (Op.getOpcode()) {
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP:
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// "Promote" the operation by extending the operand.
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return PromoteINT_TO_FP(Op);
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case ISD::FP_TO_UINT:
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case ISD::FP_TO_SINT:
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// Promote the operation by extending the operand.
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return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
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}
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// There are currently two cases of vector promotion:
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// 1) Bitcasting a vector of integers to a different type to a vector of the
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// same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
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// 2) Extending a vector of floats to a vector of the same number of larger
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// floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
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MVT VT = Op.getSimpleValueType();
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assert(Op.getNode()->getNumValues() == 1 &&
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"Can't promote a vector with multiple results!");
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MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
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SDLoc dl(Op);
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SmallVector<SDValue, 4> Operands(Op.getNumOperands());
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for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
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if (Op.getOperand(j).getValueType().isVector())
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if (Op.getOperand(j)
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.getValueType()
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.getVectorElementType()
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.isFloatingPoint() &&
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NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
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Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
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else
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Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
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else
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Operands[j] = Op.getOperand(j);
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}
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Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands);
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if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
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(VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
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NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
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return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0));
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else
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return DAG.getNode(ISD::BITCAST, dl, VT, Op);
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}
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SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
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// INT_TO_FP operations may require the input operand be promoted even
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// when the type is otherwise legal.
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EVT VT = Op.getOperand(0).getValueType();
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assert(Op.getNode()->getNumValues() == 1 &&
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"Can't promote a vector with multiple results!");
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// Normal getTypeToPromoteTo() doesn't work here, as that will promote
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// by widening the vector w/ the same element width and twice the number
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// of elements. We want the other way around, the same number of elements,
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// each twice the width.
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//
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// Increase the bitwidth of the element to the next pow-of-two
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// (which is greater than 8 bits).
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EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
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assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
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SDLoc dl(Op);
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SmallVector<SDValue, 4> Operands(Op.getNumOperands());
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unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
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ISD::SIGN_EXTEND;
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for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
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if (Op.getOperand(j).getValueType().isVector())
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Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
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else
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Operands[j] = Op.getOperand(j);
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}
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return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
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}
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// For FP_TO_INT we promote the result type to a vector type with wider
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// elements and then truncate the result. This is different from the default
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// PromoteVector which uses bitcast to promote thus assumning that the
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// promoted vector type has the same overall size.
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SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
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assert(Op.getNode()->getNumValues() == 1 &&
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"Can't promote a vector with multiple results!");
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EVT VT = Op.getValueType();
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|
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EVT NewVT;
|
|
unsigned NewOpc;
|
|
while (1) {
|
|
NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
|
|
assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
|
|
if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
|
|
NewOpc = ISD::FP_TO_SINT;
|
|
break;
|
|
}
|
|
if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
|
|
NewOpc = ISD::FP_TO_UINT;
|
|
break;
|
|
}
|
|
}
|
|
|
|
SDLoc loc(Op);
|
|
SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
|
|
return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
|
|
}
|
|
|
|
|
|
SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
|
|
SDLoc dl(Op);
|
|
LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
|
|
SDValue Chain = LD->getChain();
|
|
SDValue BasePTR = LD->getBasePtr();
|
|
EVT SrcVT = LD->getMemoryVT();
|
|
ISD::LoadExtType ExtType = LD->getExtensionType();
|
|
|
|
SmallVector<SDValue, 8> Vals;
|
|
SmallVector<SDValue, 8> LoadChains;
|
|
unsigned NumElem = SrcVT.getVectorNumElements();
|
|
|
|
EVT SrcEltVT = SrcVT.getScalarType();
|
|
EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
|
|
|
|
if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
|
|
// When elements in a vector is not byte-addressable, we cannot directly
|
|
// load each element by advancing pointer, which could only address bytes.
|
|
// Instead, we load all significant words, mask bits off, and concatenate
|
|
// them to form each element. Finally, they are extended to destination
|
|
// scalar type to build the destination vector.
|
|
EVT WideVT = TLI.getPointerTy();
|
|
|
|
assert(WideVT.isRound() &&
|
|
"Could not handle the sophisticated case when the widest integer is"
|
|
" not power of 2.");
|
|
assert(WideVT.bitsGE(SrcEltVT) &&
|
|
"Type is not legalized?");
|
|
|
|
unsigned WideBytes = WideVT.getStoreSize();
|
|
unsigned Offset = 0;
|
|
unsigned RemainingBytes = SrcVT.getStoreSize();
|
|
SmallVector<SDValue, 8> LoadVals;
|
|
|
|
while (RemainingBytes > 0) {
|
|
SDValue ScalarLoad;
|
|
unsigned LoadBytes = WideBytes;
|
|
|
|
if (RemainingBytes >= LoadBytes) {
|
|
ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
|
|
LD->getPointerInfo().getWithOffset(Offset),
|
|
LD->isVolatile(), LD->isNonTemporal(),
|
|
LD->isInvariant(),
|
|
MinAlign(LD->getAlignment(), Offset),
|
|
LD->getAAInfo());
|
|
} else {
|
|
EVT LoadVT = WideVT;
|
|
while (RemainingBytes < LoadBytes) {
|
|
LoadBytes >>= 1; // Reduce the load size by half.
|
|
LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
|
|
}
|
|
ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
|
|
LD->getPointerInfo().getWithOffset(Offset),
|
|
LoadVT, LD->isVolatile(),
|
|
LD->isNonTemporal(), LD->isInvariant(),
|
|
MinAlign(LD->getAlignment(), Offset),
|
|
LD->getAAInfo());
|
|
}
|
|
|
|
RemainingBytes -= LoadBytes;
|
|
Offset += LoadBytes;
|
|
BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
|
|
DAG.getConstant(LoadBytes, BasePTR.getValueType()));
|
|
|
|
LoadVals.push_back(ScalarLoad.getValue(0));
|
|
LoadChains.push_back(ScalarLoad.getValue(1));
|
|
}
|
|
|
|
// Extract bits, pack and extend/trunc them into destination type.
|
|
unsigned SrcEltBits = SrcEltVT.getSizeInBits();
|
|
SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, WideVT);
|
|
|
|
unsigned BitOffset = 0;
|
|
unsigned WideIdx = 0;
|
|
unsigned WideBits = WideVT.getSizeInBits();
|
|
|
|
for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
|
|
SDValue Lo, Hi, ShAmt;
|
|
|
|
if (BitOffset < WideBits) {
|
|
ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
|
|
Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
|
|
Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
|
|
}
|
|
|
|
BitOffset += SrcEltBits;
|
|
if (BitOffset >= WideBits) {
|
|
WideIdx++;
|
|
BitOffset -= WideBits;
|
|
if (BitOffset > 0) {
|
|
ShAmt = DAG.getConstant(SrcEltBits - BitOffset,
|
|
TLI.getShiftAmountTy(WideVT));
|
|
Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
|
|
Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
|
|
}
|
|
}
|
|
|
|
if (Hi.getNode())
|
|
Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
|
|
|
|
switch (ExtType) {
|
|
default: llvm_unreachable("Unknown extended-load op!");
|
|
case ISD::EXTLOAD:
|
|
Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
|
|
break;
|
|
case ISD::ZEXTLOAD:
|
|
Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
|
|
break;
|
|
case ISD::SEXTLOAD:
|
|
ShAmt = DAG.getConstant(WideBits - SrcEltBits,
|
|
TLI.getShiftAmountTy(WideVT));
|
|
Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
|
|
Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
|
|
Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
|
|
break;
|
|
}
|
|
Vals.push_back(Lo);
|
|
}
|
|
} else {
|
|
unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
|
|
|
|
for (unsigned Idx=0; Idx<NumElem; Idx++) {
|
|
SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
|
|
Op.getNode()->getValueType(0).getScalarType(),
|
|
Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
|
|
SrcVT.getScalarType(),
|
|
LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(),
|
|
MinAlign(LD->getAlignment(), Idx * Stride), LD->getAAInfo());
|
|
|
|
BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
|
|
DAG.getConstant(Stride, BasePTR.getValueType()));
|
|
|
|
Vals.push_back(ScalarLoad.getValue(0));
|
|
LoadChains.push_back(ScalarLoad.getValue(1));
|
|
}
|
|
}
|
|
|
|
SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
|
|
SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
|
|
Op.getNode()->getValueType(0), Vals);
|
|
|
|
AddLegalizedOperand(Op.getValue(0), Value);
|
|
AddLegalizedOperand(Op.getValue(1), NewChain);
|
|
|
|
return (Op.getResNo() ? NewChain : Value);
|
|
}
|
|
|
|
SDValue VectorLegalizer::ExpandStore(SDValue Op) {
|
|
SDLoc dl(Op);
|
|
StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
|
|
SDValue Chain = ST->getChain();
|
|
SDValue BasePTR = ST->getBasePtr();
|
|
SDValue Value = ST->getValue();
|
|
EVT StVT = ST->getMemoryVT();
|
|
|
|
unsigned Alignment = ST->getAlignment();
|
|
bool isVolatile = ST->isVolatile();
|
|
bool isNonTemporal = ST->isNonTemporal();
|
|
AAMDNodes AAInfo = ST->getAAInfo();
|
|
|
|
unsigned NumElem = StVT.getVectorNumElements();
|
|
// The type of the data we want to save
|
|
EVT RegVT = Value.getValueType();
|
|
EVT RegSclVT = RegVT.getScalarType();
|
|
// The type of data as saved in memory.
|
|
EVT MemSclVT = StVT.getScalarType();
|
|
|
|
// Cast floats into integers
|
|
unsigned ScalarSize = MemSclVT.getSizeInBits();
|
|
|
|
// Round odd types to the next pow of two.
|
|
if (!isPowerOf2_32(ScalarSize))
|
|
ScalarSize = NextPowerOf2(ScalarSize);
|
|
|
|
// Store Stride in bytes
|
|
unsigned Stride = ScalarSize/8;
|
|
// Extract each of the elements from the original vector
|
|
// and save them into memory individually.
|
|
SmallVector<SDValue, 8> Stores;
|
|
for (unsigned Idx = 0; Idx < NumElem; Idx++) {
|
|
SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
|
|
RegSclVT, Value, DAG.getConstant(Idx, TLI.getVectorIdxTy()));
|
|
|
|
// This scalar TruncStore may be illegal, but we legalize it later.
|
|
SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
|
|
ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
|
|
isVolatile, isNonTemporal, MinAlign(Alignment, Idx*Stride),
|
|
AAInfo);
|
|
|
|
BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
|
|
DAG.getConstant(Stride, BasePTR.getValueType()));
|
|
|
|
Stores.push_back(Store);
|
|
}
|
|
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
|
|
AddLegalizedOperand(Op, TF);
|
|
return TF;
|
|
}
|
|
|
|
SDValue VectorLegalizer::Expand(SDValue Op) {
|
|
switch (Op->getOpcode()) {
|
|
case ISD::SIGN_EXTEND_INREG:
|
|
return ExpandSEXTINREG(Op);
|
|
case ISD::ANY_EXTEND_VECTOR_INREG:
|
|
return ExpandANY_EXTEND_VECTOR_INREG(Op);
|
|
case ISD::SIGN_EXTEND_VECTOR_INREG:
|
|
return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
|
|
case ISD::ZERO_EXTEND_VECTOR_INREG:
|
|
return ExpandZERO_EXTEND_VECTOR_INREG(Op);
|
|
case ISD::BSWAP:
|
|
return ExpandBSWAP(Op);
|
|
case ISD::VSELECT:
|
|
return ExpandVSELECT(Op);
|
|
case ISD::SELECT:
|
|
return ExpandSELECT(Op);
|
|
case ISD::UINT_TO_FP:
|
|
return ExpandUINT_TO_FLOAT(Op);
|
|
case ISD::FNEG:
|
|
return ExpandFNEG(Op);
|
|
case ISD::SETCC:
|
|
return UnrollVSETCC(Op);
|
|
default:
|
|
return DAG.UnrollVectorOp(Op.getNode());
|
|
}
|
|
}
|
|
|
|
SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
|
|
// Lower a select instruction where the condition is a scalar and the
|
|
// operands are vectors. Lower this select to VSELECT and implement it
|
|
// using XOR AND OR. The selector bit is broadcasted.
|
|
EVT VT = Op.getValueType();
|
|
SDLoc DL(Op);
|
|
|
|
SDValue Mask = Op.getOperand(0);
|
|
SDValue Op1 = Op.getOperand(1);
|
|
SDValue Op2 = Op.getOperand(2);
|
|
|
|
assert(VT.isVector() && !Mask.getValueType().isVector()
|
|
&& Op1.getValueType() == Op2.getValueType() && "Invalid type");
|
|
|
|
unsigned NumElem = VT.getVectorNumElements();
|
|
|
|
// If we can't even use the basic vector operations of
|
|
// AND,OR,XOR, we will have to scalarize the op.
|
|
// Notice that the operation may be 'promoted' which means that it is
|
|
// 'bitcasted' to another type which is handled.
|
|
// Also, we need to be able to construct a splat vector using BUILD_VECTOR.
|
|
if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
|
|
TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
|
|
TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
|
|
TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
|
|
return DAG.UnrollVectorOp(Op.getNode());
|
|
|
|
// Generate a mask operand.
|
|
EVT MaskTy = VT.changeVectorElementTypeToInteger();
|
|
|
|
// What is the size of each element in the vector mask.
|
|
EVT BitTy = MaskTy.getScalarType();
|
|
|
|
Mask = DAG.getSelect(DL, BitTy, Mask,
|
|
DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy),
|
|
DAG.getConstant(0, BitTy));
|
|
|
|
// Broadcast the mask so that the entire vector is all-one or all zero.
|
|
SmallVector<SDValue, 8> Ops(NumElem, Mask);
|
|
Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
|
|
|
|
// Bitcast the operands to be the same type as the mask.
|
|
// This is needed when we select between FP types because
|
|
// the mask is a vector of integers.
|
|
Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
|
|
Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
|
|
|
|
SDValue AllOnes = DAG.getConstant(
|
|
APInt::getAllOnesValue(BitTy.getSizeInBits()), MaskTy);
|
|
SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
|
|
|
|
Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
|
|
Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
|
|
SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
|
|
return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
|
|
}
|
|
|
|
SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
|
|
EVT VT = Op.getValueType();
|
|
|
|
// Make sure that the SRA and SHL instructions are available.
|
|
if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
|
|
TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
|
|
return DAG.UnrollVectorOp(Op.getNode());
|
|
|
|
SDLoc DL(Op);
|
|
EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
|
|
|
|
unsigned BW = VT.getScalarType().getSizeInBits();
|
|
unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
|
|
SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT);
|
|
|
|
Op = Op.getOperand(0);
|
|
Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
|
|
return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
|
|
}
|
|
|
|
// Generically expand a vector anyext in register to a shuffle of the relevant
|
|
// lanes into the appropriate locations, with other lanes left undef.
|
|
SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
|
|
SDLoc DL(Op);
|
|
EVT VT = Op.getValueType();
|
|
int NumElements = VT.getVectorNumElements();
|
|
SDValue Src = Op.getOperand(0);
|
|
EVT SrcVT = Src.getValueType();
|
|
int NumSrcElements = SrcVT.getVectorNumElements();
|
|
|
|
// Build a base mask of undef shuffles.
|
|
SmallVector<int, 16> ShuffleMask;
|
|
ShuffleMask.resize(NumSrcElements, -1);
|
|
|
|
// Place the extended lanes into the correct locations.
|
|
int ExtLaneScale = NumSrcElements / NumElements;
|
|
int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0;
|
|
for (int i = 0; i < NumElements; ++i)
|
|
ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
|
|
|
|
return DAG.getNode(
|
|
ISD::BITCAST, DL, VT,
|
|
DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
|
|
}
|
|
|
|
SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
|
|
SDLoc DL(Op);
|
|
EVT VT = Op.getValueType();
|
|
SDValue Src = Op.getOperand(0);
|
|
EVT SrcVT = Src.getValueType();
|
|
|
|
// First build an any-extend node which can be legalized above when we
|
|
// recurse through it.
|
|
Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
|
|
|
|
// Now we need sign extend. Do this by shifting the elements. Even if these
|
|
// aren't legal operations, they have a better chance of being legalized
|
|
// without full scalarization than the sign extension does.
|
|
unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
|
|
unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
|
|
SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, VT);
|
|
return DAG.getNode(ISD::SRA, DL, VT,
|
|
DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
|
|
ShiftAmount);
|
|
}
|
|
|
|
// Generically expand a vector zext in register to a shuffle of the relevant
|
|
// lanes into the appropriate locations, a blend of zero into the high bits,
|
|
// and a bitcast to the wider element type.
|
|
SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
|
|
SDLoc DL(Op);
|
|
EVT VT = Op.getValueType();
|
|
int NumElements = VT.getVectorNumElements();
|
|
SDValue Src = Op.getOperand(0);
|
|
EVT SrcVT = Src.getValueType();
|
|
int NumSrcElements = SrcVT.getVectorNumElements();
|
|
|
|
// Build up a zero vector to blend into this one.
|
|
EVT SrcScalarVT = SrcVT.getScalarType();
|
|
SDValue ScalarZero = DAG.getTargetConstant(0, SrcScalarVT);
|
|
SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero);
|
|
SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands);
|
|
|
|
// Shuffle the incoming lanes into the correct position, and pull all other
|
|
// lanes from the zero vector.
|
|
SmallVector<int, 16> ShuffleMask;
|
|
ShuffleMask.reserve(NumSrcElements);
|
|
for (int i = 0; i < NumSrcElements; ++i)
|
|
ShuffleMask.push_back(i);
|
|
|
|
int ExtLaneScale = NumSrcElements / NumElements;
|
|
int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0;
|
|
for (int i = 0; i < NumElements; ++i)
|
|
ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
|
|
|
|
return DAG.getNode(ISD::BITCAST, DL, VT,
|
|
DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
|
|
}
|
|
|
|
SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
|
|
EVT VT = Op.getValueType();
|
|
|
|
// Generate a byte wise shuffle mask for the BSWAP.
|
|
SmallVector<int, 16> ShuffleMask;
|
|
int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
|
|
for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
|
|
for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
|
|
ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
|
|
|
|
EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
|
|
|
|
// Only emit a shuffle if the mask is legal.
|
|
if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
|
|
return DAG.UnrollVectorOp(Op.getNode());
|
|
|
|
SDLoc DL(Op);
|
|
Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
|
|
Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
|
|
ShuffleMask.data());
|
|
return DAG.getNode(ISD::BITCAST, DL, VT, Op);
|
|
}
|
|
|
|
SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
|
|
// Implement VSELECT in terms of XOR, AND, OR
|
|
// on platforms which do not support blend natively.
|
|
SDLoc DL(Op);
|
|
|
|
SDValue Mask = Op.getOperand(0);
|
|
SDValue Op1 = Op.getOperand(1);
|
|
SDValue Op2 = Op.getOperand(2);
|
|
|
|
EVT VT = Mask.getValueType();
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|
|
|
// If we can't even use the basic vector operations of
|
|
// AND,OR,XOR, we will have to scalarize the op.
|
|
// Notice that the operation may be 'promoted' which means that it is
|
|
// 'bitcasted' to another type which is handled.
|
|
// This operation also isn't safe with AND, OR, XOR when the boolean
|
|
// type is 0/1 as we need an all ones vector constant to mask with.
|
|
// FIXME: Sign extend 1 to all ones if thats legal on the target.
|
|
if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
|
|
TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
|
|
TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
|
|
TLI.getBooleanContents(Op1.getValueType()) !=
|
|
TargetLowering::ZeroOrNegativeOneBooleanContent)
|
|
return DAG.UnrollVectorOp(Op.getNode());
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|
|
|
// If the mask and the type are different sizes, unroll the vector op. This
|
|
// can occur when getSetCCResultType returns something that is different in
|
|
// size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
|
|
if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
|
|
return DAG.UnrollVectorOp(Op.getNode());
|
|
|
|
// Bitcast the operands to be the same type as the mask.
|
|
// This is needed when we select between FP types because
|
|
// the mask is a vector of integers.
|
|
Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
|
|
Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
|
|
|
|
SDValue AllOnes = DAG.getConstant(
|
|
APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT);
|
|
SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
|
|
|
|
Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
|
|
Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
|
|
SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
|
|
return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
|
|
}
|
|
|
|
SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
|
|
EVT VT = Op.getOperand(0).getValueType();
|
|
SDLoc DL(Op);
|
|
|
|
// Make sure that the SINT_TO_FP and SRL instructions are available.
|
|
if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
|
|
TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
|
|
return DAG.UnrollVectorOp(Op.getNode());
|
|
|
|
EVT SVT = VT.getScalarType();
|
|
assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
|
|
"Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
|
|
|
|
unsigned BW = SVT.getSizeInBits();
|
|
SDValue HalfWord = DAG.getConstant(BW/2, VT);
|
|
|
|
// Constants to clear the upper part of the word.
|
|
// Notice that we can also use SHL+SHR, but using a constant is slightly
|
|
// faster on x86.
|
|
uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
|
|
SDValue HalfWordMask = DAG.getConstant(HWMask, VT);
|
|
|
|
// Two to the power of half-word-size.
|
|
SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType());
|
|
|
|
// Clear upper part of LO, lower HI
|
|
SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
|
|
SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
|
|
|
|
// Convert hi and lo to floats
|
|
// Convert the hi part back to the upper values
|
|
SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
|
|
fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
|
|
SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
|
|
|
|
// Add the two halves
|
|
return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
|
|
}
|
|
|
|
|
|
SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
|
|
if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
|
|
SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType());
|
|
return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
|
|
Zero, Op.getOperand(0));
|
|
}
|
|
return DAG.UnrollVectorOp(Op.getNode());
|
|
}
|
|
|
|
SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
|
|
EVT VT = Op.getValueType();
|
|
unsigned NumElems = VT.getVectorNumElements();
|
|
EVT EltVT = VT.getVectorElementType();
|
|
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
|
|
EVT TmpEltVT = LHS.getValueType().getVectorElementType();
|
|
SDLoc dl(Op);
|
|
SmallVector<SDValue, 8> Ops(NumElems);
|
|
for (unsigned i = 0; i < NumElems; ++i) {
|
|
SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
|
|
DAG.getConstant(i, TLI.getVectorIdxTy()));
|
|
SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
|
|
DAG.getConstant(i, TLI.getVectorIdxTy()));
|
|
Ops[i] = DAG.getNode(ISD::SETCC, dl,
|
|
TLI.getSetCCResultType(*DAG.getContext(), TmpEltVT),
|
|
LHSElem, RHSElem, CC);
|
|
Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
|
|
DAG.getConstant(APInt::getAllOnesValue
|
|
(EltVT.getSizeInBits()), EltVT),
|
|
DAG.getConstant(0, EltVT));
|
|
}
|
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
|
|
}
|
|
|
|
}
|
|
|
|
bool SelectionDAG::LegalizeVectors() {
|
|
return VectorLegalizer(*this).Run();
|
|
}
|