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https://github.com/c64scene-ar/llvm-6502.git
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648f00c2f0
reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151402 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
1.9 KiB
LLVM
72 lines
1.9 KiB
LLVM
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=PIC
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; RUN: llc -march=mipsel -relocation-model=static < %s \
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; RUN: | FileCheck %s -check-prefix=STATIC
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; RUN: llc -march=mipsel -relocation-model=static < %s \
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; RUN: -mips-fix-global-base-reg=false | FileCheck %s -check-prefix=STATICGP
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@t1 = thread_local global i32 0, align 4
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define i32 @f1() nounwind {
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entry:
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%tmp = load i32* @t1, align 4
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ret i32 %tmp
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; CHECK: f1:
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; PIC: lw $25, %call16(__tls_get_addr)($gp)
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; PIC: addiu $4, $gp, %tlsgd(t1)
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; PIC: jalr $25
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; PIC: lw $2, 0($2)
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; STATIC: rdhwr $3, $29
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; STATIC: lui $[[R0:[0-9]+]], %tprel_hi(t1)
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; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
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; STATIC: addu $[[R2:[0-9]+]], $3, $[[R1]]
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; STATIC: lw $2, 0($[[R2]])
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}
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@t2 = external thread_local global i32
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define i32 @f2() nounwind {
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entry:
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%tmp = load i32* @t2, align 4
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ret i32 %tmp
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; CHECK: f2:
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; PIC: lw $25, %call16(__tls_get_addr)($gp)
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; PIC: addiu $4, $gp, %tlsgd(t2)
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; PIC: jalr $25
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; PIC: lw $2, 0($2)
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; STATICGP: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp)
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; STATICGP: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
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; STATICGP: lw ${{[0-9]+}}, %gottprel(t2)($[[GP]])
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; STATIC: lui $gp, %hi(__gnu_local_gp)
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; STATIC: addiu $gp, $gp, %lo(__gnu_local_gp)
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; STATIC: rdhwr $3, $29
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; STATIC: lw $[[R0:[0-9]+]], %gottprel(t2)($gp)
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; STATIC: addu $[[R1:[0-9]+]], $3, $[[R0]]
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; STATIC: lw $2, 0($[[R1]])
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}
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@f3.i = internal thread_local unnamed_addr global i32 1, align 4
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define i32 @f3() nounwind {
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entry:
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; CHECK: f3:
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; PIC: addiu $4, $gp, %tlsldm(f3.i)
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; PIC: jalr $25
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; PIC: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i)
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; PIC: addu $[[R1:[0-9]+]], $[[R0]], $2
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; PIC: lw ${{[0-9]+}}, %dtprel_lo(f3.i)($[[R1]])
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%0 = load i32* @f3.i, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @f3.i, align 4
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ret i32 %inc
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}
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