Evan Cheng bf57b52ba4 Add a CodeGenOpt::Less level to match -O1. It'll be used by clients which do not want post-regalloc scheduling. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84272 91177308-0d34-0410-b5e6-96231b3b80d8

2009-10-16 21:02:20 +00:00

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SubtargetFeature.h

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Target.td

Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When

2009-10-01 08:21:18 +00:00

TargetAsmParser.h

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TargetCallingConv.td

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TargetData.h

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TargetELFWriterInfo.h

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TargetFrameInfo.h

Use explicit structs instead of std::pair to map callee saved regs to spill slots.

2009-09-27 17:58:47 +00:00

TargetInstrDesc.h

Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When

2009-10-01 08:21:18 +00:00

TargetInstrInfo.h

Revert the kludge in 76703. I got a clean

2009-10-12 18:49:00 +00:00

TargetInstrItineraries.h

Make the end-of-itinerary mark explicit. Some cleanup.

2009-09-24 20:22:50 +00:00

TargetIntrinsicInfo.h

Clean up TargetIntrinsicInfo API. Add pure virtual methods.

2009-10-15 18:49:26 +00:00

TargetJITInfo.h

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TargetLowering.h

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TargetLoweringObjectFile.h

Use OutStreamer.SwitchSection instead of writing out textual section directives.

2009-09-30 22:25:37 +00:00

TargetMachine.h

Add a CodeGenOpt::Less level to match -O1. It'll be used by clients which do not want post-regalloc scheduling.

2009-10-16 21:02:20 +00:00

TargetMachOWriterInfo.h

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TargetOptions.h

Implement the JIT side of the GDB JIT debugging interface. To enable this

2009-09-20 23:52:43 +00:00

TargetRegisterInfo.h

Add a const qualifier.

2009-10-09 22:09:05 +00:00

TargetRegistry.h

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TargetSchedule.td

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TargetSelect.h

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TargetSelectionDAG.td

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TargetSubtarget.h

Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.

2009-09-30 00:10:16 +00:00