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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
2.4 KiB
LLVM
77 lines
2.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}fmul_f32:
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; R600: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
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; SI: v_mul_f32
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define void @fmul_f32(float addrspace(1)* %out, float %a, float %b) {
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entry:
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%0 = fmul float %a, %b
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store float %0, float addrspace(1)* %out
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ret void
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}
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declare float @llvm.R600.load.input(i32) readnone
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declare void @llvm.AMDGPU.store.output(float, i32)
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; FUNC-LABEL: {{^}}fmul_v2f32:
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; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}
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; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}
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; SI: v_mul_f32
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; SI: v_mul_f32
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define void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
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entry:
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%0 = fmul <2 x float> %a, %b
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store <2 x float> %0, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fmul_v4f32:
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; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_mul_f32
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; SI: v_mul_f32
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; SI: v_mul_f32
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; SI: v_mul_f32
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define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float>, <4 x float> addrspace(1) * %in
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%b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
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%result = fmul <4 x float> %a, %b
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_mul_2_k:
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; SI: v_mul_f32
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; SI-NOT: v_mul_f32
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; SI: s_endpgm
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define void @test_mul_2_k(float addrspace(1)* %out, float %x) #0 {
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%y = fmul float %x, 2.0
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%z = fmul float %y, 3.0
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store float %z, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_mul_2_k_inv:
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; SI: v_mul_f32
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; SI-NOT: v_mul_f32
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; SI-NOT: v_mad_f32
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; SI: s_endpgm
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define void @test_mul_2_k_inv(float addrspace(1)* %out, float %x) #0 {
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%y = fmul float %x, 3.0
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%z = fmul float %y, 2.0
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store float %z, float addrspace(1)* %out
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ret void
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}
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attributes #0 = { "less-precise-fpmad"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" }
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