mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 17:29:19 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
1381 lines
40 KiB
C++
1381 lines
40 KiB
C++
//===-- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIDefines.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCParser/MCAsmParser.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCTargetAsmParser.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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namespace {
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struct OptionalOperand;
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class AMDGPUOperand : public MCParsedAsmOperand {
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enum KindTy {
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Token,
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Immediate,
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Register,
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Expression
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} Kind;
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SMLoc StartLoc, EndLoc;
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public:
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AMDGPUOperand(enum KindTy K) : MCParsedAsmOperand(), Kind(K) {}
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MCContext *Ctx;
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enum ImmTy {
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ImmTyNone,
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ImmTyDSOffset0,
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ImmTyDSOffset1,
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ImmTyGDS,
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ImmTyOffset,
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ImmTyGLC,
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ImmTySLC,
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ImmTyTFE,
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ImmTyClamp,
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ImmTyOMod
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};
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struct TokOp {
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const char *Data;
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unsigned Length;
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};
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struct ImmOp {
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bool IsFPImm;
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ImmTy Type;
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int64_t Val;
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};
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struct RegOp {
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unsigned RegNo;
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int Modifiers;
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const MCRegisterInfo *TRI;
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bool IsForcedVOP3;
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};
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union {
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TokOp Tok;
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ImmOp Imm;
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RegOp Reg;
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const MCExpr *Expr;
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};
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void addImmOperands(MCInst &Inst, unsigned N) const {
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Inst.addOperand(MCOperand::createImm(getImm()));
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}
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StringRef getToken() const {
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return StringRef(Tok.Data, Tok.Length);
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}
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void addRegOperands(MCInst &Inst, unsigned N) const {
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Inst.addOperand(MCOperand::createReg(getReg()));
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}
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void addRegOrImmOperands(MCInst &Inst, unsigned N) const {
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if (isReg())
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addRegOperands(Inst, N);
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else
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addImmOperands(Inst, N);
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}
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void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {
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Inst.addOperand(MCOperand::createImm(
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Reg.Modifiers == -1 ? 0 : Reg.Modifiers));
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addRegOperands(Inst, N);
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}
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void addSoppBrTargetOperands(MCInst &Inst, unsigned N) const {
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if (isImm())
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addImmOperands(Inst, N);
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else {
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assert(isExpr());
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Inst.addOperand(MCOperand::createExpr(Expr));
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}
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}
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bool defaultTokenHasSuffix() const {
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StringRef Token(Tok.Data, Tok.Length);
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return Token.endswith("_e32") || Token.endswith("_e64");
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}
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bool isToken() const override {
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return Kind == Token;
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}
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bool isImm() const override {
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return Kind == Immediate;
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}
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bool isInlineImm() const {
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float F = BitsToFloat(Imm.Val);
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// TODO: Add 0.5pi for VI
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return isImm() && ((Imm.Val <= 64 && Imm.Val >= -16) ||
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(F == 0.0 || F == 0.5 || F == -0.5 || F == 1.0 || F == -1.0 ||
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F == 2.0 || F == -2.0 || F == 4.0 || F == -4.0));
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}
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bool isDSOffset0() const {
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assert(isImm());
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return Imm.Type == ImmTyDSOffset0;
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}
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bool isDSOffset1() const {
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assert(isImm());
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return Imm.Type == ImmTyDSOffset1;
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}
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int64_t getImm() const {
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return Imm.Val;
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}
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enum ImmTy getImmTy() const {
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assert(isImm());
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return Imm.Type;
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}
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bool isRegKind() const {
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return Kind == Register;
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}
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bool isReg() const override {
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return Kind == Register && Reg.Modifiers == -1;
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}
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bool isRegWithInputMods() const {
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return Kind == Register && (Reg.IsForcedVOP3 || Reg.Modifiers != -1);
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}
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void setModifiers(unsigned Mods) {
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assert(isReg());
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Reg.Modifiers = Mods;
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}
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bool hasModifiers() const {
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assert(isRegKind());
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return Reg.Modifiers != -1;
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}
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unsigned getReg() const override {
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return Reg.RegNo;
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}
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bool isRegOrImm() const {
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return isReg() || isImm();
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}
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bool isRegClass(unsigned RCID) const {
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return Reg.TRI->getRegClass(RCID).contains(getReg());
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}
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bool isSCSrc32() const {
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return isInlineImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID));
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}
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bool isSSrc32() const {
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return isImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID));
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}
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bool isSSrc64() const {
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return isImm() || isInlineImm() ||
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(isReg() && isRegClass(AMDGPU::SReg_64RegClassID));
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}
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bool isVCSrc32() const {
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return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID));
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}
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bool isVCSrc64() const {
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return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID));
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}
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bool isVSrc32() const {
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return isImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID));
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}
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bool isVSrc64() const {
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return isImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID));
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}
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bool isMem() const override {
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return false;
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}
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bool isExpr() const {
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return Kind == Expression;
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}
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bool isSoppBrTarget() const {
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return isExpr() || isImm();
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}
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SMLoc getStartLoc() const override {
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return StartLoc;
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}
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SMLoc getEndLoc() const override {
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return EndLoc;
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}
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void print(raw_ostream &OS) const override { }
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static std::unique_ptr<AMDGPUOperand> CreateImm(int64_t Val, SMLoc Loc,
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enum ImmTy Type = ImmTyNone,
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bool IsFPImm = false) {
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auto Op = llvm::make_unique<AMDGPUOperand>(Immediate);
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Op->Imm.Val = Val;
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Op->Imm.IsFPImm = IsFPImm;
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Op->Imm.Type = Type;
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Op->StartLoc = Loc;
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Op->EndLoc = Loc;
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return Op;
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}
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static std::unique_ptr<AMDGPUOperand> CreateToken(StringRef Str, SMLoc Loc,
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bool HasExplicitEncodingSize = true) {
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auto Res = llvm::make_unique<AMDGPUOperand>(Token);
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Res->Tok.Data = Str.data();
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Res->Tok.Length = Str.size();
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Res->StartLoc = Loc;
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Res->EndLoc = Loc;
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return Res;
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}
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static std::unique_ptr<AMDGPUOperand> CreateReg(unsigned RegNo, SMLoc S,
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SMLoc E,
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const MCRegisterInfo *TRI,
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bool ForceVOP3) {
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auto Op = llvm::make_unique<AMDGPUOperand>(Register);
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Op->Reg.RegNo = RegNo;
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Op->Reg.TRI = TRI;
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Op->Reg.Modifiers = -1;
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Op->Reg.IsForcedVOP3 = ForceVOP3;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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static std::unique_ptr<AMDGPUOperand> CreateExpr(const class MCExpr *Expr, SMLoc S) {
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auto Op = llvm::make_unique<AMDGPUOperand>(Expression);
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Op->Expr = Expr;
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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bool isDSOffset() const;
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bool isDSOffset01() const;
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bool isSWaitCnt() const;
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bool isMubufOffset() const;
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};
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class AMDGPUAsmParser : public MCTargetAsmParser {
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MCSubtargetInfo &STI;
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const MCInstrInfo &MII;
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MCAsmParser &Parser;
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unsigned ForcedEncodingSize;
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/// @name Auto-generated Match Functions
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/// {
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#define GET_ASSEMBLER_HEADER
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#include "AMDGPUGenAsmMatcher.inc"
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/// }
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public:
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AMDGPUAsmParser(MCSubtargetInfo &STI, MCAsmParser &_Parser,
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const MCInstrInfo &MII,
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const MCTargetOptions &Options)
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: MCTargetAsmParser(), STI(STI), MII(MII), Parser(_Parser),
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ForcedEncodingSize(0){
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if (STI.getFeatureBits().none()) {
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// Set default features.
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STI.ToggleFeature("SOUTHERN_ISLANDS");
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}
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setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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}
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unsigned getForcedEncodingSize() const {
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return ForcedEncodingSize;
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}
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void setForcedEncodingSize(unsigned Size) {
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ForcedEncodingSize = Size;
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}
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bool isForcedVOP3() const {
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return ForcedEncodingSize == 64;
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}
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bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
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unsigned checkTargetMatchPredicate(MCInst &Inst) override;
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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OperandVector &Operands, MCStreamer &Out,
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uint64_t &ErrorInfo,
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bool MatchingInlineAsm) override;
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bool ParseDirective(AsmToken DirectiveID) override;
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OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
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bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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SMLoc NameLoc, OperandVector &Operands) override;
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OperandMatchResultTy parseIntWithPrefix(const char *Prefix, int64_t &Int,
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int64_t Default = 0);
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OperandMatchResultTy parseIntWithPrefix(const char *Prefix,
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OperandVector &Operands,
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enum AMDGPUOperand::ImmTy ImmTy =
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AMDGPUOperand::ImmTyNone);
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OperandMatchResultTy parseNamedBit(const char *Name, OperandVector &Operands,
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enum AMDGPUOperand::ImmTy ImmTy =
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AMDGPUOperand::ImmTyNone);
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OperandMatchResultTy parseOptionalOps(
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const ArrayRef<OptionalOperand> &OptionalOps,
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OperandVector &Operands);
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void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
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void cvtDS(MCInst &Inst, const OperandVector &Operands);
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OperandMatchResultTy parseDSOptionalOps(OperandVector &Operands);
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OperandMatchResultTy parseDSOff01OptionalOps(OperandVector &Operands);
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OperandMatchResultTy parseDSOffsetOptional(OperandVector &Operands);
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bool parseCnt(int64_t &IntVal);
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OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
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OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
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OperandMatchResultTy parseFlatOptionalOps(OperandVector &Operands);
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OperandMatchResultTy parseFlatAtomicOptionalOps(OperandVector &Operands);
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void cvtFlat(MCInst &Inst, const OperandVector &Operands);
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void cvtMubuf(MCInst &Inst, const OperandVector &Operands);
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OperandMatchResultTy parseOffset(OperandVector &Operands);
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OperandMatchResultTy parseMubufOptionalOps(OperandVector &Operands);
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OperandMatchResultTy parseGLC(OperandVector &Operands);
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OperandMatchResultTy parseSLC(OperandVector &Operands);
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OperandMatchResultTy parseTFE(OperandVector &Operands);
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OperandMatchResultTy parseDMask(OperandVector &Operands);
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OperandMatchResultTy parseUNorm(OperandVector &Operands);
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OperandMatchResultTy parseR128(OperandVector &Operands);
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void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
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OperandMatchResultTy parseVOP3OptionalOps(OperandVector &Operands);
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};
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struct OptionalOperand {
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const char *Name;
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AMDGPUOperand::ImmTy Type;
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bool IsBit;
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int64_t Default;
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bool (*ConvertResult)(int64_t&);
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};
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}
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static unsigned getRegClass(bool IsVgpr, unsigned RegWidth) {
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if (IsVgpr) {
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switch (RegWidth) {
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default: llvm_unreachable("Unknown register width");
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case 1: return AMDGPU::VGPR_32RegClassID;
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case 2: return AMDGPU::VReg_64RegClassID;
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case 3: return AMDGPU::VReg_96RegClassID;
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case 4: return AMDGPU::VReg_128RegClassID;
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case 8: return AMDGPU::VReg_256RegClassID;
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case 16: return AMDGPU::VReg_512RegClassID;
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}
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}
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switch (RegWidth) {
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default: llvm_unreachable("Unknown register width");
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case 1: return AMDGPU::SGPR_32RegClassID;
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case 2: return AMDGPU::SGPR_64RegClassID;
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case 4: return AMDGPU::SReg_128RegClassID;
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case 8: return AMDGPU::SReg_256RegClassID;
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case 16: return AMDGPU::SReg_512RegClassID;
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}
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}
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static unsigned getRegForName(const StringRef &RegName) {
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return StringSwitch<unsigned>(RegName)
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.Case("exec", AMDGPU::EXEC)
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.Case("vcc", AMDGPU::VCC)
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.Case("flat_scr", AMDGPU::FLAT_SCR)
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.Case("m0", AMDGPU::M0)
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.Case("scc", AMDGPU::SCC)
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.Case("flat_scr_lo", AMDGPU::FLAT_SCR_LO)
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.Case("flat_scr_hi", AMDGPU::FLAT_SCR_HI)
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.Case("vcc_lo", AMDGPU::VCC_LO)
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.Case("vcc_hi", AMDGPU::VCC_HI)
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.Case("exec_lo", AMDGPU::EXEC_LO)
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.Case("exec_hi", AMDGPU::EXEC_HI)
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.Default(0);
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}
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bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
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const AsmToken Tok = Parser.getTok();
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StartLoc = Tok.getLoc();
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EndLoc = Tok.getEndLoc();
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const StringRef &RegName = Tok.getString();
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RegNo = getRegForName(RegName);
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if (RegNo) {
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Parser.Lex();
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return false;
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}
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// Match vgprs and sgprs
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if (RegName[0] != 's' && RegName[0] != 'v')
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return true;
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bool IsVgpr = RegName[0] == 'v';
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unsigned RegWidth;
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unsigned RegIndexInClass;
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if (RegName.size() > 1) {
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// We have a 32-bit register
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RegWidth = 1;
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if (RegName.substr(1).getAsInteger(10, RegIndexInClass))
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return true;
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Parser.Lex();
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} else {
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// We have a register greater than 32-bits.
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int64_t RegLo, RegHi;
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Parser.Lex();
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if (getLexer().isNot(AsmToken::LBrac))
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return true;
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Parser.Lex();
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if (getParser().parseAbsoluteExpression(RegLo))
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return true;
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if (getLexer().isNot(AsmToken::Colon))
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return true;
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Parser.Lex();
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if (getParser().parseAbsoluteExpression(RegHi))
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return true;
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if (getLexer().isNot(AsmToken::RBrac))
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return true;
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Parser.Lex();
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RegWidth = (RegHi - RegLo) + 1;
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if (IsVgpr) {
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// VGPR registers aren't aligned.
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RegIndexInClass = RegLo;
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} else {
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// SGPR registers are aligned. Max alignment is 4 dwords.
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RegIndexInClass = RegLo / std::min(RegWidth, 4u);
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}
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}
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const MCRegisterInfo *TRC = getContext().getRegisterInfo();
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unsigned RC = getRegClass(IsVgpr, RegWidth);
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if (RegIndexInClass > TRC->getRegClass(RC).getNumRegs())
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return true;
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RegNo = TRC->getRegClass(RC).getRegister(RegIndexInClass);
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return false;
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}
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unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
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if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) ||
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(getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)))
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return Match_InvalidOperand;
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return Match_Success;
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}
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|
|
|
|
|
bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
|
|
OperandVector &Operands,
|
|
MCStreamer &Out,
|
|
uint64_t &ErrorInfo,
|
|
bool MatchingInlineAsm) {
|
|
MCInst Inst;
|
|
|
|
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
|
|
default: break;
|
|
case Match_Success:
|
|
Inst.setLoc(IDLoc);
|
|
Out.EmitInstruction(Inst, STI);
|
|
return false;
|
|
case Match_MissingFeature:
|
|
return Error(IDLoc, "instruction not supported on this GPU");
|
|
|
|
case Match_MnemonicFail:
|
|
return Error(IDLoc, "unrecognized instruction mnemonic");
|
|
|
|
case Match_InvalidOperand: {
|
|
SMLoc ErrorLoc = IDLoc;
|
|
if (ErrorInfo != ~0ULL) {
|
|
if (ErrorInfo >= Operands.size()) {
|
|
if (isForcedVOP3()) {
|
|
// If 64-bit encoding has been forced we can end up with no
|
|
// clamp or omod operands if none of the registers have modifiers,
|
|
// so we need to add these to the operand list.
|
|
AMDGPUOperand &LastOp =
|
|
((AMDGPUOperand &)*Operands[Operands.size() - 1]);
|
|
if (LastOp.isRegKind() ||
|
|
(LastOp.isImm() &&
|
|
LastOp.getImmTy() != AMDGPUOperand::ImmTyNone)) {
|
|
SMLoc S = Parser.getTok().getLoc();
|
|
Operands.push_back(AMDGPUOperand::CreateImm(0, S,
|
|
AMDGPUOperand::ImmTyClamp));
|
|
Operands.push_back(AMDGPUOperand::CreateImm(0, S,
|
|
AMDGPUOperand::ImmTyOMod));
|
|
bool Res = MatchAndEmitInstruction(IDLoc, Opcode, Operands,
|
|
Out, ErrorInfo,
|
|
MatchingInlineAsm);
|
|
if (!Res)
|
|
return Res;
|
|
}
|
|
|
|
}
|
|
return Error(IDLoc, "too few operands for instruction");
|
|
}
|
|
|
|
ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();
|
|
if (ErrorLoc == SMLoc())
|
|
ErrorLoc = IDLoc;
|
|
}
|
|
return Error(ErrorLoc, "invalid operand for instruction");
|
|
}
|
|
}
|
|
llvm_unreachable("Implement any new match types added!");
|
|
}
|
|
|
|
bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
|
|
return true;
|
|
}
|
|
|
|
static bool operandsHaveModifiers(const OperandVector &Operands) {
|
|
|
|
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
|
|
const AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]);
|
|
if (Op.isRegKind() && Op.hasModifiers())
|
|
return true;
|
|
if (Op.isImm() && (Op.getImmTy() == AMDGPUOperand::ImmTyOMod ||
|
|
Op.getImmTy() == AMDGPUOperand::ImmTyClamp))
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
|
|
|
|
// Try to parse with a custom parser
|
|
OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
|
|
|
|
// If we successfully parsed the operand or if there as an error parsing,
|
|
// we are done.
|
|
//
|
|
// If we are parsing after we reach EndOfStatement then this means we
|
|
// are appending default values to the Operands list. This is only done
|
|
// by custom parser, so we shouldn't continue on to the generic parsing.
|
|
if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail ||
|
|
getLexer().is(AsmToken::EndOfStatement))
|
|
return ResTy;
|
|
|
|
bool Negate = false, Abs = false;
|
|
if (getLexer().getKind()== AsmToken::Minus) {
|
|
Parser.Lex();
|
|
Negate = true;
|
|
}
|
|
|
|
if (getLexer().getKind() == AsmToken::Pipe) {
|
|
Parser.Lex();
|
|
Abs = true;
|
|
}
|
|
|
|
switch(getLexer().getKind()) {
|
|
case AsmToken::Integer: {
|
|
SMLoc S = Parser.getTok().getLoc();
|
|
int64_t IntVal;
|
|
if (getParser().parseAbsoluteExpression(IntVal))
|
|
return MatchOperand_ParseFail;
|
|
APInt IntVal32(32, IntVal);
|
|
if (IntVal32.getSExtValue() != IntVal) {
|
|
Error(S, "invalid immediate: only 32-bit values are legal");
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
|
|
IntVal = IntVal32.getSExtValue();
|
|
if (Negate)
|
|
IntVal *= -1;
|
|
Operands.push_back(AMDGPUOperand::CreateImm(IntVal, S));
|
|
return MatchOperand_Success;
|
|
}
|
|
case AsmToken::Real: {
|
|
// FIXME: We should emit an error if a double precisions floating-point
|
|
// value is used. I'm not sure the best way to detect this.
|
|
SMLoc S = Parser.getTok().getLoc();
|
|
int64_t IntVal;
|
|
if (getParser().parseAbsoluteExpression(IntVal))
|
|
return MatchOperand_ParseFail;
|
|
|
|
APFloat F((float)BitsToDouble(IntVal));
|
|
if (Negate)
|
|
F.changeSign();
|
|
Operands.push_back(
|
|
AMDGPUOperand::CreateImm(F.bitcastToAPInt().getZExtValue(), S));
|
|
return MatchOperand_Success;
|
|
}
|
|
case AsmToken::Identifier: {
|
|
SMLoc S, E;
|
|
unsigned RegNo;
|
|
if (!ParseRegister(RegNo, S, E)) {
|
|
|
|
bool HasModifiers = operandsHaveModifiers(Operands);
|
|
unsigned Modifiers = 0;
|
|
|
|
if (Negate)
|
|
Modifiers |= 0x1;
|
|
|
|
if (Abs) {
|
|
if (getLexer().getKind() != AsmToken::Pipe)
|
|
return MatchOperand_ParseFail;
|
|
Parser.Lex();
|
|
Modifiers |= 0x2;
|
|
}
|
|
|
|
if (Modifiers && !HasModifiers) {
|
|
// We are adding a modifier to src1 or src2 and previous sources
|
|
// don't have modifiers, so we need to go back and empty modifers
|
|
// for each previous source.
|
|
for (unsigned PrevRegIdx = Operands.size() - 1; PrevRegIdx > 1;
|
|
--PrevRegIdx) {
|
|
|
|
AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[PrevRegIdx]);
|
|
RegOp.setModifiers(0);
|
|
}
|
|
}
|
|
|
|
|
|
Operands.push_back(AMDGPUOperand::CreateReg(
|
|
RegNo, S, E, getContext().getRegisterInfo(),
|
|
isForcedVOP3()));
|
|
|
|
if (HasModifiers || Modifiers) {
|
|
AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[Operands.size() - 1]);
|
|
RegOp.setModifiers(Modifiers);
|
|
|
|
}
|
|
} else {
|
|
Operands.push_back(AMDGPUOperand::CreateToken(Parser.getTok().getString(),
|
|
S));
|
|
Parser.Lex();
|
|
}
|
|
return MatchOperand_Success;
|
|
}
|
|
default:
|
|
return MatchOperand_NoMatch;
|
|
}
|
|
}
|
|
|
|
bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
|
|
StringRef Name,
|
|
SMLoc NameLoc, OperandVector &Operands) {
|
|
|
|
// Clear any forced encodings from the previous instruction.
|
|
setForcedEncodingSize(0);
|
|
|
|
if (Name.endswith("_e64"))
|
|
setForcedEncodingSize(64);
|
|
else if (Name.endswith("_e32"))
|
|
setForcedEncodingSize(32);
|
|
|
|
// Add the instruction mnemonic
|
|
Operands.push_back(AMDGPUOperand::CreateToken(Name, NameLoc));
|
|
|
|
while (!getLexer().is(AsmToken::EndOfStatement)) {
|
|
AMDGPUAsmParser::OperandMatchResultTy Res = parseOperand(Operands, Name);
|
|
|
|
// Eat the comma or space if there is one.
|
|
if (getLexer().is(AsmToken::Comma))
|
|
Parser.Lex();
|
|
|
|
switch (Res) {
|
|
case MatchOperand_Success: break;
|
|
case MatchOperand_ParseFail: return Error(getLexer().getLoc(),
|
|
"failed parsing operand.");
|
|
case MatchOperand_NoMatch: return Error(getLexer().getLoc(),
|
|
"not a valid operand.");
|
|
}
|
|
}
|
|
|
|
// Once we reach end of statement, continue parsing so we can add default
|
|
// values for optional arguments.
|
|
AMDGPUAsmParser::OperandMatchResultTy Res;
|
|
while ((Res = parseOperand(Operands, Name)) != MatchOperand_NoMatch) {
|
|
if (Res != MatchOperand_Success)
|
|
return Error(getLexer().getLoc(), "failed parsing operand.");
|
|
}
|
|
return false;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Utility functions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &Int,
|
|
int64_t Default) {
|
|
|
|
// We are at the end of the statement, and this is a default argument, so
|
|
// use a default value.
|
|
if (getLexer().is(AsmToken::EndOfStatement)) {
|
|
Int = Default;
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
switch(getLexer().getKind()) {
|
|
default: return MatchOperand_NoMatch;
|
|
case AsmToken::Identifier: {
|
|
StringRef OffsetName = Parser.getTok().getString();
|
|
if (!OffsetName.equals(Prefix))
|
|
return MatchOperand_NoMatch;
|
|
|
|
Parser.Lex();
|
|
if (getLexer().isNot(AsmToken::Colon))
|
|
return MatchOperand_ParseFail;
|
|
|
|
Parser.Lex();
|
|
if (getLexer().isNot(AsmToken::Integer))
|
|
return MatchOperand_ParseFail;
|
|
|
|
if (getParser().parseAbsoluteExpression(Int))
|
|
return MatchOperand_ParseFail;
|
|
break;
|
|
}
|
|
}
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
|
|
enum AMDGPUOperand::ImmTy ImmTy) {
|
|
|
|
SMLoc S = Parser.getTok().getLoc();
|
|
int64_t Offset = 0;
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy Res = parseIntWithPrefix(Prefix, Offset);
|
|
if (Res != MatchOperand_Success)
|
|
return Res;
|
|
|
|
Operands.push_back(AMDGPUOperand::CreateImm(Offset, S, ImmTy));
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands,
|
|
enum AMDGPUOperand::ImmTy ImmTy) {
|
|
int64_t Bit = 0;
|
|
SMLoc S = Parser.getTok().getLoc();
|
|
|
|
// We are at the end of the statement, and this is a default argument, so
|
|
// use a default value.
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
switch(getLexer().getKind()) {
|
|
case AsmToken::Identifier: {
|
|
StringRef Tok = Parser.getTok().getString();
|
|
if (Tok == Name) {
|
|
Bit = 1;
|
|
Parser.Lex();
|
|
} else if (Tok.startswith("no") && Tok.endswith(Name)) {
|
|
Bit = 0;
|
|
Parser.Lex();
|
|
} else {
|
|
return MatchOperand_NoMatch;
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
return MatchOperand_NoMatch;
|
|
}
|
|
}
|
|
|
|
Operands.push_back(AMDGPUOperand::CreateImm(Bit, S, ImmTy));
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
static bool operandsHasOptionalOp(const OperandVector &Operands,
|
|
const OptionalOperand &OOp) {
|
|
for (unsigned i = 0; i < Operands.size(); i++) {
|
|
const AMDGPUOperand &ParsedOp = ((const AMDGPUOperand &)*Operands[i]);
|
|
if ((ParsedOp.isImm() && ParsedOp.getImmTy() == OOp.Type) ||
|
|
(ParsedOp.isToken() && ParsedOp.getToken() == OOp.Name))
|
|
return true;
|
|
|
|
}
|
|
return false;
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseOptionalOps(const ArrayRef<OptionalOperand> &OptionalOps,
|
|
OperandVector &Operands) {
|
|
SMLoc S = Parser.getTok().getLoc();
|
|
for (const OptionalOperand &Op : OptionalOps) {
|
|
if (operandsHasOptionalOp(Operands, Op))
|
|
continue;
|
|
AMDGPUAsmParser::OperandMatchResultTy Res;
|
|
int64_t Value;
|
|
if (Op.IsBit) {
|
|
Res = parseNamedBit(Op.Name, Operands, Op.Type);
|
|
if (Res == MatchOperand_NoMatch)
|
|
continue;
|
|
return Res;
|
|
}
|
|
|
|
Res = parseIntWithPrefix(Op.Name, Value, Op.Default);
|
|
|
|
if (Res == MatchOperand_NoMatch)
|
|
continue;
|
|
|
|
if (Res != MatchOperand_Success)
|
|
return Res;
|
|
|
|
if (Op.ConvertResult && !Op.ConvertResult(Value)) {
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
|
|
Operands.push_back(AMDGPUOperand::CreateImm(Value, S, Op.Type));
|
|
return MatchOperand_Success;
|
|
}
|
|
return MatchOperand_NoMatch;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ds
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
static const OptionalOperand DSOptionalOps [] = {
|
|
{"offset", AMDGPUOperand::ImmTyOffset, false, 0, nullptr},
|
|
{"gds", AMDGPUOperand::ImmTyGDS, true, 0, nullptr}
|
|
};
|
|
|
|
static const OptionalOperand DSOptionalOpsOff01 [] = {
|
|
{"offset0", AMDGPUOperand::ImmTyDSOffset0, false, 0, nullptr},
|
|
{"offset1", AMDGPUOperand::ImmTyDSOffset1, false, 0, nullptr},
|
|
{"gds", AMDGPUOperand::ImmTyGDS, true, 0, nullptr}
|
|
};
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseDSOptionalOps(OperandVector &Operands) {
|
|
return parseOptionalOps(DSOptionalOps, Operands);
|
|
}
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseDSOff01OptionalOps(OperandVector &Operands) {
|
|
return parseOptionalOps(DSOptionalOpsOff01, Operands);
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseDSOffsetOptional(OperandVector &Operands) {
|
|
SMLoc S = Parser.getTok().getLoc();
|
|
AMDGPUAsmParser::OperandMatchResultTy Res =
|
|
parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset);
|
|
if (Res == MatchOperand_NoMatch) {
|
|
Operands.push_back(AMDGPUOperand::CreateImm(0, S,
|
|
AMDGPUOperand::ImmTyOffset));
|
|
Res = MatchOperand_Success;
|
|
}
|
|
return Res;
|
|
}
|
|
|
|
bool AMDGPUOperand::isDSOffset() const {
|
|
return isImm() && isUInt<16>(getImm());
|
|
}
|
|
|
|
bool AMDGPUOperand::isDSOffset01() const {
|
|
return isImm() && isUInt<8>(getImm());
|
|
}
|
|
|
|
void AMDGPUAsmParser::cvtDSOffset01(MCInst &Inst,
|
|
const OperandVector &Operands) {
|
|
|
|
std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
|
|
|
|
for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
|
|
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
|
|
|
|
// Add the register arguments
|
|
if (Op.isReg()) {
|
|
Op.addRegOperands(Inst, 1);
|
|
continue;
|
|
}
|
|
|
|
// Handle optional arguments
|
|
OptionalIdx[Op.getImmTy()] = i;
|
|
}
|
|
|
|
unsigned Offset0Idx = OptionalIdx[AMDGPUOperand::ImmTyDSOffset0];
|
|
unsigned Offset1Idx = OptionalIdx[AMDGPUOperand::ImmTyDSOffset1];
|
|
unsigned GDSIdx = OptionalIdx[AMDGPUOperand::ImmTyGDS];
|
|
|
|
((AMDGPUOperand &)*Operands[Offset0Idx]).addImmOperands(Inst, 1); // offset0
|
|
((AMDGPUOperand &)*Operands[Offset1Idx]).addImmOperands(Inst, 1); // offset1
|
|
((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds
|
|
Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
|
|
}
|
|
|
|
void AMDGPUAsmParser::cvtDS(MCInst &Inst, const OperandVector &Operands) {
|
|
|
|
std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
|
|
bool GDSOnly = false;
|
|
|
|
for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
|
|
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
|
|
|
|
// Add the register arguments
|
|
if (Op.isReg()) {
|
|
Op.addRegOperands(Inst, 1);
|
|
continue;
|
|
}
|
|
|
|
if (Op.isToken() && Op.getToken() == "gds") {
|
|
GDSOnly = true;
|
|
continue;
|
|
}
|
|
|
|
// Handle optional arguments
|
|
OptionalIdx[Op.getImmTy()] = i;
|
|
}
|
|
|
|
unsigned OffsetIdx = OptionalIdx[AMDGPUOperand::ImmTyOffset];
|
|
((AMDGPUOperand &)*Operands[OffsetIdx]).addImmOperands(Inst, 1); // offset
|
|
|
|
if (!GDSOnly) {
|
|
unsigned GDSIdx = OptionalIdx[AMDGPUOperand::ImmTyGDS];
|
|
((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds
|
|
}
|
|
Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// s_waitcnt
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
|
|
StringRef CntName = Parser.getTok().getString();
|
|
int64_t CntVal;
|
|
|
|
Parser.Lex();
|
|
if (getLexer().isNot(AsmToken::LParen))
|
|
return true;
|
|
|
|
Parser.Lex();
|
|
if (getLexer().isNot(AsmToken::Integer))
|
|
return true;
|
|
|
|
if (getParser().parseAbsoluteExpression(CntVal))
|
|
return true;
|
|
|
|
if (getLexer().isNot(AsmToken::RParen))
|
|
return true;
|
|
|
|
Parser.Lex();
|
|
if (getLexer().is(AsmToken::Amp) || getLexer().is(AsmToken::Comma))
|
|
Parser.Lex();
|
|
|
|
int CntShift;
|
|
int CntMask;
|
|
|
|
if (CntName == "vmcnt") {
|
|
CntMask = 0xf;
|
|
CntShift = 0;
|
|
} else if (CntName == "expcnt") {
|
|
CntMask = 0x7;
|
|
CntShift = 4;
|
|
} else if (CntName == "lgkmcnt") {
|
|
CntMask = 0x7;
|
|
CntShift = 8;
|
|
} else {
|
|
return true;
|
|
}
|
|
|
|
IntVal &= ~(CntMask << CntShift);
|
|
IntVal |= (CntVal << CntShift);
|
|
return false;
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {
|
|
// Disable all counters by default.
|
|
// vmcnt [3:0]
|
|
// expcnt [6:4]
|
|
// lgkmcnt [10:8]
|
|
int64_t CntVal = 0x77f;
|
|
SMLoc S = Parser.getTok().getLoc();
|
|
|
|
switch(getLexer().getKind()) {
|
|
default: return MatchOperand_ParseFail;
|
|
case AsmToken::Integer:
|
|
// The operand can be an integer value.
|
|
if (getParser().parseAbsoluteExpression(CntVal))
|
|
return MatchOperand_ParseFail;
|
|
break;
|
|
|
|
case AsmToken::Identifier:
|
|
do {
|
|
if (parseCnt(CntVal))
|
|
return MatchOperand_ParseFail;
|
|
} while(getLexer().isNot(AsmToken::EndOfStatement));
|
|
break;
|
|
}
|
|
Operands.push_back(AMDGPUOperand::CreateImm(CntVal, S));
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
bool AMDGPUOperand::isSWaitCnt() const {
|
|
return isImm();
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// sopp branch targets
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {
|
|
SMLoc S = Parser.getTok().getLoc();
|
|
|
|
switch (getLexer().getKind()) {
|
|
default: return MatchOperand_ParseFail;
|
|
case AsmToken::Integer: {
|
|
int64_t Imm;
|
|
if (getParser().parseAbsoluteExpression(Imm))
|
|
return MatchOperand_ParseFail;
|
|
Operands.push_back(AMDGPUOperand::CreateImm(Imm, S));
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
case AsmToken::Identifier:
|
|
Operands.push_back(AMDGPUOperand::CreateExpr(
|
|
MCSymbolRefExpr::create(getContext().getOrCreateSymbol(
|
|
Parser.getTok().getString()), getContext()), S));
|
|
Parser.Lex();
|
|
return MatchOperand_Success;
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// flat
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
static const OptionalOperand FlatOptionalOps [] = {
|
|
{"glc", AMDGPUOperand::ImmTyGLC, true, 0, nullptr},
|
|
{"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr},
|
|
{"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
|
|
};
|
|
|
|
static const OptionalOperand FlatAtomicOptionalOps [] = {
|
|
{"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr},
|
|
{"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
|
|
};
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseFlatOptionalOps(OperandVector &Operands) {
|
|
return parseOptionalOps(FlatOptionalOps, Operands);
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseFlatAtomicOptionalOps(OperandVector &Operands) {
|
|
return parseOptionalOps(FlatAtomicOptionalOps, Operands);
|
|
}
|
|
|
|
void AMDGPUAsmParser::cvtFlat(MCInst &Inst,
|
|
const OperandVector &Operands) {
|
|
std::map<AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
|
|
|
|
for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
|
|
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
|
|
|
|
// Add the register arguments
|
|
if (Op.isReg()) {
|
|
Op.addRegOperands(Inst, 1);
|
|
continue;
|
|
}
|
|
|
|
// Handle 'glc' token which is sometimes hard-coded into the
|
|
// asm string. There are no MCInst operands for these.
|
|
if (Op.isToken())
|
|
continue;
|
|
|
|
// Handle optional arguments
|
|
OptionalIdx[Op.getImmTy()] = i;
|
|
|
|
}
|
|
|
|
// flat atomic instructions don't have a glc argument.
|
|
if (OptionalIdx.count(AMDGPUOperand::ImmTyGLC)) {
|
|
unsigned GLCIdx = OptionalIdx[AMDGPUOperand::ImmTyGLC];
|
|
((AMDGPUOperand &)*Operands[GLCIdx]).addImmOperands(Inst, 1);
|
|
}
|
|
|
|
unsigned SLCIdx = OptionalIdx[AMDGPUOperand::ImmTySLC];
|
|
unsigned TFEIdx = OptionalIdx[AMDGPUOperand::ImmTyTFE];
|
|
|
|
((AMDGPUOperand &)*Operands[SLCIdx]).addImmOperands(Inst, 1);
|
|
((AMDGPUOperand &)*Operands[TFEIdx]).addImmOperands(Inst, 1);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// mubuf
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
static const OptionalOperand MubufOptionalOps [] = {
|
|
{"offset", AMDGPUOperand::ImmTyOffset, false, 0, nullptr},
|
|
{"glc", AMDGPUOperand::ImmTyGLC, true, 0, nullptr},
|
|
{"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr},
|
|
{"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
|
|
};
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseMubufOptionalOps(OperandVector &Operands) {
|
|
return parseOptionalOps(MubufOptionalOps, Operands);
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseOffset(OperandVector &Operands) {
|
|
return parseIntWithPrefix("offset", Operands);
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseGLC(OperandVector &Operands) {
|
|
return parseNamedBit("glc", Operands);
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseSLC(OperandVector &Operands) {
|
|
return parseNamedBit("slc", Operands);
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseTFE(OperandVector &Operands) {
|
|
return parseNamedBit("tfe", Operands);
|
|
}
|
|
|
|
bool AMDGPUOperand::isMubufOffset() const {
|
|
return isImm() && isUInt<12>(getImm());
|
|
}
|
|
|
|
void AMDGPUAsmParser::cvtMubuf(MCInst &Inst,
|
|
const OperandVector &Operands) {
|
|
std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
|
|
|
|
for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
|
|
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
|
|
|
|
// Add the register arguments
|
|
if (Op.isReg()) {
|
|
Op.addRegOperands(Inst, 1);
|
|
continue;
|
|
}
|
|
|
|
// Handle the case where soffset is an immediate
|
|
if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {
|
|
Op.addImmOperands(Inst, 1);
|
|
continue;
|
|
}
|
|
|
|
// Handle tokens like 'offen' which are sometimes hard-coded into the
|
|
// asm string. There are no MCInst operands for these.
|
|
if (Op.isToken()) {
|
|
continue;
|
|
}
|
|
assert(Op.isImm());
|
|
|
|
// Handle optional arguments
|
|
OptionalIdx[Op.getImmTy()] = i;
|
|
}
|
|
|
|
assert(OptionalIdx.size() == 4);
|
|
|
|
unsigned OffsetIdx = OptionalIdx[AMDGPUOperand::ImmTyOffset];
|
|
unsigned GLCIdx = OptionalIdx[AMDGPUOperand::ImmTyGLC];
|
|
unsigned SLCIdx = OptionalIdx[AMDGPUOperand::ImmTySLC];
|
|
unsigned TFEIdx = OptionalIdx[AMDGPUOperand::ImmTyTFE];
|
|
|
|
((AMDGPUOperand &)*Operands[OffsetIdx]).addImmOperands(Inst, 1);
|
|
((AMDGPUOperand &)*Operands[GLCIdx]).addImmOperands(Inst, 1);
|
|
((AMDGPUOperand &)*Operands[SLCIdx]).addImmOperands(Inst, 1);
|
|
((AMDGPUOperand &)*Operands[TFEIdx]).addImmOperands(Inst, 1);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// mimg
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseDMask(OperandVector &Operands) {
|
|
return parseIntWithPrefix("dmask", Operands);
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseUNorm(OperandVector &Operands) {
|
|
return parseNamedBit("unorm", Operands);
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseR128(OperandVector &Operands) {
|
|
return parseNamedBit("r128", Operands);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// vop3
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
static bool ConvertOmodMul(int64_t &Mul) {
|
|
if (Mul != 1 && Mul != 2 && Mul != 4)
|
|
return false;
|
|
|
|
Mul >>= 1;
|
|
return true;
|
|
}
|
|
|
|
static bool ConvertOmodDiv(int64_t &Div) {
|
|
if (Div == 1) {
|
|
Div = 0;
|
|
return true;
|
|
}
|
|
|
|
if (Div == 2) {
|
|
Div = 3;
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static const OptionalOperand VOP3OptionalOps [] = {
|
|
{"clamp", AMDGPUOperand::ImmTyClamp, true, 0, nullptr},
|
|
{"mul", AMDGPUOperand::ImmTyOMod, false, 1, ConvertOmodMul},
|
|
{"div", AMDGPUOperand::ImmTyOMod, false, 1, ConvertOmodDiv},
|
|
};
|
|
|
|
static bool isVOP3(OperandVector &Operands) {
|
|
if (operandsHaveModifiers(Operands))
|
|
return true;
|
|
|
|
AMDGPUOperand &DstOp = ((AMDGPUOperand&)*Operands[1]);
|
|
|
|
if (DstOp.isReg() && DstOp.isRegClass(AMDGPU::SGPR_64RegClassID))
|
|
return true;
|
|
|
|
if (Operands.size() >= 5)
|
|
return true;
|
|
|
|
if (Operands.size() > 3) {
|
|
AMDGPUOperand &Src1Op = ((AMDGPUOperand&)*Operands[3]);
|
|
if (Src1Op.getReg() && (Src1Op.isRegClass(AMDGPU::SReg_32RegClassID) ||
|
|
Src1Op.isRegClass(AMDGPU::SReg_64RegClassID)))
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy
|
|
AMDGPUAsmParser::parseVOP3OptionalOps(OperandVector &Operands) {
|
|
|
|
// The value returned by this function may change after parsing
|
|
// an operand so store the original value here.
|
|
bool HasModifiers = operandsHaveModifiers(Operands);
|
|
|
|
bool IsVOP3 = isVOP3(Operands);
|
|
if (HasModifiers || IsVOP3 ||
|
|
getLexer().isNot(AsmToken::EndOfStatement) ||
|
|
getForcedEncodingSize() == 64) {
|
|
|
|
AMDGPUAsmParser::OperandMatchResultTy Res =
|
|
parseOptionalOps(VOP3OptionalOps, Operands);
|
|
|
|
if (!HasModifiers && Res == MatchOperand_Success) {
|
|
// We have added a modifier operation, so we need to make sure all
|
|
// previous register operands have modifiers
|
|
for (unsigned i = 2, e = Operands.size(); i != e; ++i) {
|
|
AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]);
|
|
if (Op.isReg())
|
|
Op.setModifiers(0);
|
|
}
|
|
}
|
|
return Res;
|
|
}
|
|
return MatchOperand_NoMatch;
|
|
}
|
|
|
|
void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
|
|
((AMDGPUOperand &)*Operands[1]).addRegOperands(Inst, 1);
|
|
unsigned i = 2;
|
|
|
|
std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
|
|
|
|
if (operandsHaveModifiers(Operands)) {
|
|
for (unsigned e = Operands.size(); i != e; ++i) {
|
|
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
|
|
|
|
if (Op.isRegWithInputMods()) {
|
|
((AMDGPUOperand &)*Operands[i]).addRegWithInputModsOperands(Inst, 2);
|
|
continue;
|
|
}
|
|
OptionalIdx[Op.getImmTy()] = i;
|
|
}
|
|
|
|
unsigned ClampIdx = OptionalIdx[AMDGPUOperand::ImmTyClamp];
|
|
unsigned OModIdx = OptionalIdx[AMDGPUOperand::ImmTyOMod];
|
|
|
|
((AMDGPUOperand &)*Operands[ClampIdx]).addImmOperands(Inst, 1);
|
|
((AMDGPUOperand &)*Operands[OModIdx]).addImmOperands(Inst, 1);
|
|
} else {
|
|
for (unsigned e = Operands.size(); i != e; ++i)
|
|
((AMDGPUOperand &)*Operands[i]).addRegOrImmOperands(Inst, 1);
|
|
}
|
|
}
|
|
|
|
/// Force static initialization.
|
|
extern "C" void LLVMInitializeAMDGPUAsmParser() {
|
|
RegisterMCAsmParser<AMDGPUAsmParser> A(TheAMDGPUTarget);
|
|
RegisterMCAsmParser<AMDGPUAsmParser> B(TheGCNTarget);
|
|
}
|
|
|
|
#define GET_REGISTER_MATCHER
|
|
#define GET_MATCHER_IMPLEMENTATION
|
|
#include "AMDGPUGenAsmMatcher.inc"
|
|
|