mirror of
https://github.com/c64scene-ar/llvm-6502.git
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c09eeec0eb
are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts, such as the PowerPC 970. This speeds up 189.lucas from 81.99 to 32.64 seconds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23250 91177308-0d34-0410-b5e6-96231b3b80d8
769 lines
31 KiB
C++
769 lines
31 KiB
C++
//===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Implementation ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the PPC32ISelLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC32ISelLowering.h"
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#include "PPC32TargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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using namespace llvm;
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PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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// Fold away setcc operations if possible.
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setSetCCIsExpensive();
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// Set up the register classes.
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addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
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addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
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addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
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// PowerPC has no intrinsics for these particular operations
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setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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// PowerPC has an i16 but no i8 (or i1) SEXTLOAD
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setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
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setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
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// PowerPC has no SREM/UREM instructions
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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// We don't support sin/cos/sqrt/fmod
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::SREM , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::SREM , MVT::f32, Expand);
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// If we're enabling GP optimizations, use hardware square root
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if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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}
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// PowerPC does not have CTPOP or CTTZ
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setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
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// PowerPC does not have Select
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::f32, Expand);
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setOperationAction(ISD::SELECT, MVT::f64, Expand);
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// PowerPC wants to turn select_cc of FP into fsel when possible.
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
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// PowerPC wants to expand i64 shifts itself.
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setOperationAction(ISD::SHL, MVT::i64, Custom);
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setOperationAction(ISD::SRL, MVT::i64, Custom);
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setOperationAction(ISD::SRA, MVT::i64, Custom);
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// PowerPC does not have BRCOND* which requires SetCC
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
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// PowerPC does not have FP_TO_UINT
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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// PowerPC does not have [U|S]INT_TO_FP
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
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// 64 bit PowerPC implementations have instructions to facilitate conversion
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// between i64 and fp.
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if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
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}
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setSetCCResultContents(ZeroOrOneSetCCResult);
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computeRegisterProperties();
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}
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/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
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static bool isFloatingPointZero(SDOperand Op) {
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if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
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return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
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else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
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// Maybe this has already been legalized into the constant pool?
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
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if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
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return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
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}
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return false;
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default: assert(0 && "Wasn't expecting to be able to lower this!");
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case ISD::FP_TO_SINT: {
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assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
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switch (Op.getValueType()) {
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default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
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case MVT::i32:
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Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Op.getOperand(0));
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break;
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case MVT::i64:
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Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Op.getOperand(0));
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break;
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}
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int FrameIdx =
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DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
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SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
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Op, FI, DAG.getSrcValue(0));
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if (Op.getOpcode() == PPCISD::FCTIDZ) {
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Op = DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
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} else {
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FI = DAG.getNode(ISD::ADD, MVT::i32, FI, DAG.getConstant(4, MVT::i32));
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Op = DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0));
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}
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return Op;
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}
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case ISD::SINT_TO_FP: {
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assert(MVT::i64 == Op.getOperand(0).getValueType() &&
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"Unhandled SINT_TO_FP type in custom expander!");
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int FrameIdx =
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DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
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SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
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Op.getOperand(0), FI, DAG.getSrcValue(0));
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SDOperand LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
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SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, LD);
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if (MVT::f32 == Op.getValueType())
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FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
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return FP;
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}
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case ISD::SELECT_CC: {
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// Turn FP only select_cc's into fsel instructions.
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if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
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!MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
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break;
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
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// Cannot handle SETEQ/SETNE.
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if (CC == ISD::SETEQ || CC == ISD::SETNE) break;
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MVT::ValueType ResVT = Op.getValueType();
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MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
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SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
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SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
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// If the RHS of the comparison is a 0.0, we don't need to do the
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// subtraction at all.
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if (isFloatingPointZero(RHS))
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switch (CC) {
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default: assert(0 && "Invalid FSEL condition"); abort();
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case ISD::SETULT:
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case ISD::SETLT:
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std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
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case ISD::SETUGE:
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case ISD::SETGE:
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return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
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case ISD::SETUGT:
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case ISD::SETGT:
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std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
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case ISD::SETULE:
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case ISD::SETLE:
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return DAG.getNode(PPCISD::FSEL, ResVT,
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DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
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}
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switch (CC) {
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default: assert(0 && "Invalid FSEL condition"); abort();
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case ISD::SETULT:
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case ISD::SETLT:
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return DAG.getNode(PPCISD::FSEL, ResVT,
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DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV, TV);
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case ISD::SETUGE:
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case ISD::SETGE:
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return DAG.getNode(PPCISD::FSEL, ResVT,
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DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV, FV);
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case ISD::SETUGT:
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case ISD::SETGT:
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return DAG.getNode(PPCISD::FSEL, ResVT,
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DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV, TV);
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case ISD::SETULE:
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case ISD::SETLE:
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return DAG.getNode(PPCISD::FSEL, ResVT,
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DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV, FV);
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}
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break;
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}
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case ISD::SHL: {
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assert(Op.getValueType() == MVT::i64 &&
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Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
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// The generic code does a fine job expanding shift by a constant.
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if (isa<ConstantSDNode>(Op.getOperand(1))) break;
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// Otherwise, expand into a bunch of logical ops. Note that these ops
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// depend on the PPC behavior for oversized shift amounts.
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SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
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DAG.getConstant(0, MVT::i32));
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SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
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DAG.getConstant(1, MVT::i32));
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SDOperand Amt = Op.getOperand(1);
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SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
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DAG.getConstant(32, MVT::i32), Amt);
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SDOperand Tmp2 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Amt);
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SDOperand Tmp3 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Tmp1);
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SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
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SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
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DAG.getConstant(-32U, MVT::i32));
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SDOperand Tmp6 = DAG.getNode(ISD::SHL, MVT::i32, Lo, Tmp5);
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SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
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SDOperand OutLo = DAG.getNode(ISD::SHL, MVT::i32, Lo, Amt);
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return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
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}
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case ISD::SRL: {
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assert(Op.getValueType() == MVT::i64 &&
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Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
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// The generic code does a fine job expanding shift by a constant.
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if (isa<ConstantSDNode>(Op.getOperand(1))) break;
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// Otherwise, expand into a bunch of logical ops. Note that these ops
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// depend on the PPC behavior for oversized shift amounts.
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SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
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DAG.getConstant(0, MVT::i32));
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SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
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DAG.getConstant(1, MVT::i32));
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SDOperand Amt = Op.getOperand(1);
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SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
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DAG.getConstant(32, MVT::i32), Amt);
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SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
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SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
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SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
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SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
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DAG.getConstant(-32U, MVT::i32));
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SDOperand Tmp6 = DAG.getNode(ISD::SRL, MVT::i32, Hi, Tmp5);
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SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
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SDOperand OutHi = DAG.getNode(ISD::SRL, MVT::i32, Hi, Amt);
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return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
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}
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case ISD::SRA: {
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assert(Op.getValueType() == MVT::i64 &&
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Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
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// The generic code does a fine job expanding shift by a constant.
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if (isa<ConstantSDNode>(Op.getOperand(1))) break;
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// Otherwise, expand into a bunch of logical ops, followed by a select_cc.
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SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
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DAG.getConstant(0, MVT::i32));
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SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
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DAG.getConstant(1, MVT::i32));
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SDOperand Amt = Op.getOperand(1);
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SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
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DAG.getConstant(32, MVT::i32), Amt);
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SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
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SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
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SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
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SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
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DAG.getConstant(-32U, MVT::i32));
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SDOperand Tmp6 = DAG.getNode(ISD::SRA, MVT::i32, Hi, Tmp5);
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SDOperand OutHi = DAG.getNode(ISD::SRA, MVT::i32, Hi, Amt);
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SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
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Tmp4, Tmp6, ISD::SETLE);
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return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
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}
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}
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return SDOperand();
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}
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std::vector<SDOperand>
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PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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//
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// add beautiful description of PPC stack frame format, or at least some docs
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//
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineBasicBlock& BB = MF.front();
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std::vector<SDOperand> ArgValues;
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// Due to the rather complicated nature of the PowerPC ABI, rather than a
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// fixed size array of physical args, for the sake of simplicity let the STL
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// handle tracking them for us.
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std::vector<unsigned> argVR, argPR, argOp;
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unsigned ArgOffset = 24;
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unsigned GPR_remaining = 8;
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unsigned FPR_remaining = 13;
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unsigned GPR_idx = 0, FPR_idx = 0;
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static const unsigned GPR[] = {
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PPC::R3, PPC::R4, PPC::R5, PPC::R6,
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PPC::R7, PPC::R8, PPC::R9, PPC::R10,
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};
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static const unsigned FPR[] = {
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PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
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PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
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};
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// Add DAG nodes to load the arguments... On entry to a function on PPC,
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// the arguments start at offset 24, although they are likely to be passed
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// in registers.
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
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SDOperand newroot, argt;
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unsigned ObjSize;
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bool needsLoad = false;
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bool ArgLive = !I->use_empty();
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MVT::ValueType ObjectVT = getValueType(I->getType());
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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ObjSize = 4;
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if (!ArgLive) break;
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if (GPR_remaining > 0) {
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MF.addLiveIn(GPR[GPR_idx]);
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argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
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GPR[GPR_idx], MVT::i32);
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if (ObjectVT != MVT::i32) {
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unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
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: ISD::AssertZext;
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argt = DAG.getNode(AssertOp, MVT::i32, argt,
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DAG.getValueType(ObjectVT));
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argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
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}
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} else {
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needsLoad = true;
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}
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break;
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case MVT::i64: ObjSize = 8;
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if (!ArgLive) break;
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if (GPR_remaining > 0) {
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SDOperand argHi, argLo;
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MF.addLiveIn(GPR[GPR_idx]);
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argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
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// If we have two or more remaining argument registers, then both halves
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// of the i64 can be sourced from there. Otherwise, the lower half will
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// have to come off the stack. This can happen when an i64 is preceded
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// by 28 bytes of arguments.
|
|
if (GPR_remaining > 1) {
|
|
MF.addLiveIn(GPR[GPR_idx+1]);
|
|
argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32);
|
|
} else {
|
|
int FI = MFI->CreateFixedObject(4, ArgOffset+4);
|
|
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
|
|
argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
|
|
DAG.getSrcValue(NULL));
|
|
}
|
|
// Build the outgoing arg thingy
|
|
argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
|
|
newroot = argLo;
|
|
} else {
|
|
needsLoad = true;
|
|
}
|
|
break;
|
|
case MVT::f32:
|
|
case MVT::f64:
|
|
ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
|
|
if (!ArgLive) break;
|
|
if (FPR_remaining > 0) {
|
|
MF.addLiveIn(FPR[FPR_idx]);
|
|
argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
|
|
FPR[FPR_idx], ObjectVT);
|
|
--FPR_remaining;
|
|
++FPR_idx;
|
|
} else {
|
|
needsLoad = true;
|
|
}
|
|
break;
|
|
}
|
|
|
|
// We need to load the argument to a virtual register if we determined above
|
|
// that we ran out of physical registers of the appropriate type
|
|
if (needsLoad) {
|
|
unsigned SubregOffset = 0;
|
|
if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
|
|
if (ObjectVT == MVT::i16) SubregOffset = 2;
|
|
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
|
|
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
|
|
FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
|
|
DAG.getConstant(SubregOffset, MVT::i32));
|
|
argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
|
|
DAG.getSrcValue(NULL));
|
|
}
|
|
|
|
// Every 4 bytes of argument space consumes one of the GPRs available for
|
|
// argument passing.
|
|
if (GPR_remaining > 0) {
|
|
unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
|
|
GPR_remaining -= delta;
|
|
GPR_idx += delta;
|
|
}
|
|
ArgOffset += ObjSize;
|
|
if (newroot.Val)
|
|
DAG.setRoot(newroot.getValue(1));
|
|
|
|
ArgValues.push_back(argt);
|
|
}
|
|
|
|
// If the function takes variable number of arguments, make a frame index for
|
|
// the start of the first vararg value... for expansion of llvm.va_start.
|
|
if (F.isVarArg()) {
|
|
VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
|
|
SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
|
|
// If this function is vararg, store any remaining integer argument regs
|
|
// to their spots on the stack so that they may be loaded by deferencing the
|
|
// result of va_next.
|
|
std::vector<SDOperand> MemOps;
|
|
for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
|
|
MF.addLiveIn(GPR[GPR_idx]);
|
|
SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
|
|
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
|
|
Val, FIN, DAG.getSrcValue(NULL));
|
|
MemOps.push_back(Store);
|
|
// Increment the address by four for the next argument to store
|
|
SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
|
|
FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
|
|
}
|
|
DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
|
|
}
|
|
|
|
// Finally, inform the code generator which regs we return values in.
|
|
switch (getValueType(F.getReturnType())) {
|
|
default: assert(0 && "Unknown type!");
|
|
case MVT::isVoid: break;
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
MF.addLiveOut(PPC::R3);
|
|
break;
|
|
case MVT::i64:
|
|
MF.addLiveOut(PPC::R3);
|
|
MF.addLiveOut(PPC::R4);
|
|
break;
|
|
case MVT::f32:
|
|
case MVT::f64:
|
|
MF.addLiveOut(PPC::F1);
|
|
break;
|
|
}
|
|
|
|
return ArgValues;
|
|
}
|
|
|
|
std::pair<SDOperand, SDOperand>
|
|
PPC32TargetLowering::LowerCallTo(SDOperand Chain,
|
|
const Type *RetTy, bool isVarArg,
|
|
unsigned CallingConv, bool isTailCall,
|
|
SDOperand Callee, ArgListTy &Args,
|
|
SelectionDAG &DAG) {
|
|
// args_to_use will accumulate outgoing args for the ISD::CALL case in
|
|
// SelectExpr to use to put the arguments in the appropriate registers.
|
|
std::vector<SDOperand> args_to_use;
|
|
|
|
// Count how many bytes are to be pushed on the stack, including the linkage
|
|
// area, and parameter passing area.
|
|
unsigned NumBytes = 24;
|
|
|
|
if (Args.empty()) {
|
|
Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
|
|
DAG.getConstant(NumBytes, getPointerTy()));
|
|
} else {
|
|
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
|
switch (getValueType(Args[i].second)) {
|
|
default: assert(0 && "Unknown value type!");
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
case MVT::f32:
|
|
NumBytes += 4;
|
|
break;
|
|
case MVT::i64:
|
|
case MVT::f64:
|
|
NumBytes += 8;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Just to be safe, we'll always reserve the full 24 bytes of linkage area
|
|
// plus 32 bytes of argument space in case any called code gets funky on us.
|
|
// (Required by ABI to support var arg)
|
|
if (NumBytes < 56) NumBytes = 56;
|
|
|
|
// Adjust the stack pointer for the new arguments...
|
|
// These operations are automatically eliminated by the prolog/epilog pass
|
|
Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
|
|
DAG.getConstant(NumBytes, getPointerTy()));
|
|
|
|
// Set up a copy of the stack pointer for use loading and storing any
|
|
// arguments that may not fit in the registers available for argument
|
|
// passing.
|
|
SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
|
|
PPC::R1, MVT::i32);
|
|
|
|
// Figure out which arguments are going to go in registers, and which in
|
|
// memory. Also, if this is a vararg function, floating point operations
|
|
// must be stored to our stack, and loaded into integer regs as well, if
|
|
// any integer regs are available for argument passing.
|
|
unsigned ArgOffset = 24;
|
|
unsigned GPR_remaining = 8;
|
|
unsigned FPR_remaining = 13;
|
|
|
|
std::vector<SDOperand> MemOps;
|
|
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
|
// PtrOff will be used to store the current argument to the stack if a
|
|
// register cannot be found for it.
|
|
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
|
|
MVT::ValueType ArgVT = getValueType(Args[i].second);
|
|
|
|
switch (ArgVT) {
|
|
default: assert(0 && "Unexpected ValueType for argument!");
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
// Promote the integer to 32 bits. If the input type is signed use a
|
|
// sign extend, otherwise use a zero extend.
|
|
if (Args[i].second->isSigned())
|
|
Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
|
|
else
|
|
Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
|
|
// FALL THROUGH
|
|
case MVT::i32:
|
|
if (GPR_remaining > 0) {
|
|
args_to_use.push_back(Args[i].first);
|
|
--GPR_remaining;
|
|
} else {
|
|
MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
Args[i].first, PtrOff,
|
|
DAG.getSrcValue(NULL)));
|
|
}
|
|
ArgOffset += 4;
|
|
break;
|
|
case MVT::i64:
|
|
// If we have one free GPR left, we can place the upper half of the i64
|
|
// in it, and store the other half to the stack. If we have two or more
|
|
// free GPRs, then we can pass both halves of the i64 in registers.
|
|
if (GPR_remaining > 0) {
|
|
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
|
|
Args[i].first, DAG.getConstant(1, MVT::i32));
|
|
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
|
|
Args[i].first, DAG.getConstant(0, MVT::i32));
|
|
args_to_use.push_back(Hi);
|
|
--GPR_remaining;
|
|
if (GPR_remaining > 0) {
|
|
args_to_use.push_back(Lo);
|
|
--GPR_remaining;
|
|
} else {
|
|
SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
|
|
MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
Lo, PtrOff, DAG.getSrcValue(NULL)));
|
|
}
|
|
} else {
|
|
MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
Args[i].first, PtrOff,
|
|
DAG.getSrcValue(NULL)));
|
|
}
|
|
ArgOffset += 8;
|
|
break;
|
|
case MVT::f32:
|
|
case MVT::f64:
|
|
if (FPR_remaining > 0) {
|
|
args_to_use.push_back(Args[i].first);
|
|
--FPR_remaining;
|
|
if (isVarArg) {
|
|
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
Args[i].first, PtrOff,
|
|
DAG.getSrcValue(NULL));
|
|
MemOps.push_back(Store);
|
|
// Float varargs are always shadowed in available integer registers
|
|
if (GPR_remaining > 0) {
|
|
SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
|
|
DAG.getSrcValue(NULL));
|
|
MemOps.push_back(Load);
|
|
args_to_use.push_back(Load);
|
|
--GPR_remaining;
|
|
}
|
|
if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
|
|
SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
|
|
SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
|
|
DAG.getSrcValue(NULL));
|
|
MemOps.push_back(Load);
|
|
args_to_use.push_back(Load);
|
|
--GPR_remaining;
|
|
}
|
|
} else {
|
|
// If we have any FPRs remaining, we may also have GPRs remaining.
|
|
// Args passed in FPRs consume either 1 (f32) or 2 (f64) available
|
|
// GPRs.
|
|
if (GPR_remaining > 0) {
|
|
args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
|
|
--GPR_remaining;
|
|
}
|
|
if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
|
|
args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
|
|
--GPR_remaining;
|
|
}
|
|
}
|
|
} else {
|
|
MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
Args[i].first, PtrOff,
|
|
DAG.getSrcValue(NULL)));
|
|
}
|
|
ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
|
|
break;
|
|
}
|
|
}
|
|
if (!MemOps.empty())
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
|
|
}
|
|
|
|
std::vector<MVT::ValueType> RetVals;
|
|
MVT::ValueType RetTyVT = getValueType(RetTy);
|
|
MVT::ValueType ActualRetTyVT = RetTyVT;
|
|
if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
|
|
ActualRetTyVT = MVT::i32; // Promote result to i32.
|
|
|
|
if (RetTyVT != MVT::isVoid)
|
|
RetVals.push_back(ActualRetTyVT);
|
|
RetVals.push_back(MVT::Other);
|
|
|
|
SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
|
|
Chain, Callee, args_to_use), 0);
|
|
Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
|
|
Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
|
|
DAG.getConstant(NumBytes, getPointerTy()));
|
|
SDOperand RetVal = TheCall;
|
|
|
|
// If the result is a small value, add a note so that we keep track of the
|
|
// information about whether it is sign or zero extended.
|
|
if (RetTyVT != ActualRetTyVT) {
|
|
RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
|
|
MVT::i32, RetVal, DAG.getValueType(RetTyVT));
|
|
RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
|
|
}
|
|
|
|
return std::make_pair(RetVal, Chain);
|
|
}
|
|
|
|
SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
|
|
Value *VAListV, SelectionDAG &DAG) {
|
|
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
|
// memory location argument.
|
|
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
|
|
return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
|
|
DAG.getSrcValue(VAListV));
|
|
}
|
|
|
|
std::pair<SDOperand,SDOperand>
|
|
PPC32TargetLowering::LowerVAArg(SDOperand Chain,
|
|
SDOperand VAListP, Value *VAListV,
|
|
const Type *ArgTy, SelectionDAG &DAG) {
|
|
MVT::ValueType ArgVT = getValueType(ArgTy);
|
|
|
|
SDOperand VAList =
|
|
DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
|
|
SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
|
|
unsigned Amt;
|
|
if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
|
|
Amt = 4;
|
|
else {
|
|
assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
|
|
"Other types should have been promoted for varargs!");
|
|
Amt = 8;
|
|
}
|
|
VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
|
|
DAG.getConstant(Amt, VAList.getValueType()));
|
|
Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
VAList, VAListP, DAG.getSrcValue(VAListV));
|
|
return std::make_pair(Result, Chain);
|
|
}
|
|
|
|
|
|
std::pair<SDOperand, SDOperand> PPC32TargetLowering::
|
|
LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
|
|
SelectionDAG &DAG) {
|
|
assert(0 && "LowerFrameReturnAddress unimplemented");
|
|
abort();
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
PPC32TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
|
|
MachineBasicBlock *BB) {
|
|
assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
|
|
MI->getOpcode() == PPC::SELECT_CC_FP) &&
|
|
"Unexpected instr type to insert");
|
|
|
|
// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
|
|
// control-flow pattern. The incoming instruction knows the destination vreg
|
|
// to set, the condition code register to branch on, the true/false values to
|
|
// select between, and a branch opcode to use.
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
ilist<MachineBasicBlock>::iterator It = BB;
|
|
++It;
|
|
|
|
// thisMBB:
|
|
// ...
|
|
// TrueVal = ...
|
|
// cmpTY ccX, r1, r2
|
|
// bCC copy1MBB
|
|
// fallthrough --> copy0MBB
|
|
MachineBasicBlock *thisMBB = BB;
|
|
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
|
|
BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
|
|
.addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
|
|
MachineFunction *F = BB->getParent();
|
|
F->getBasicBlockList().insert(It, copy0MBB);
|
|
F->getBasicBlockList().insert(It, sinkMBB);
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(copy0MBB);
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
// copy0MBB:
|
|
// %FalseValue = ...
|
|
// # fallthrough to sinkMBB
|
|
BB = copy0MBB;
|
|
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
// sinkMBB:
|
|
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
|
// ...
|
|
BB = sinkMBB;
|
|
BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
|
|
.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
|
|
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
|
|
|
|
delete MI; // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|
|
|