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bfe8afaaec
live across BBs before register allocation. This miscompiled 197.parser when a cmp + b are optimized to a cbnz instruction even though the CPSR def is live-in a successor. cbnz r6, LBB89_12 ... LBB89_12: ble LBB89_1 The fix consists of two parts. 1) Teach LiveVariables that some unallocatable registers might be liveouts so don't mark their last use as kill if they are. 2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional branch does not kill CPSR. rdar://10676853 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148168 91177308-0d34-0410-b5e6-96231b3b80d8 |
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ARM | ||
CBackend | ||
CellSPU | ||
CPP | ||
Generic | ||
Hexagon | ||
MBlaze | ||
Mips | ||
MSP430 | ||
PowerPC | ||
PTX | ||
SPARC | ||
Thumb | ||
Thumb2 | ||
X86 | ||
XCore |