Vikram S. Adve bfebd79dd1 (1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6343 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 00:07:13 +00:00
2003-05-26 23:41:13 +00:00
2003-05-25 16:52:41 +00:00
2003-05-25 16:52:41 +00:00
Description
LLVM backend for 6502
277 MiB
Languages
C++ 48.7%
LLVM 38.5%
Assembly 10.2%
C 0.9%
Python 0.4%
Other 1.2%