mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28310 91177308-0d34-0410-b5e6-96231b3b80d8
140 lines
4.0 KiB
C++
140 lines
4.0 KiB
C++
//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the ARM target.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMTargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Debug.h"
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#include <iostream>
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#include <set>
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using namespace llvm;
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namespace ARMISD {
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enum {
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FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
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RET_FLAG,
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};
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}
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namespace {
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class ARMTargetLowering : public TargetLowering {
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public:
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ARMTargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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unsigned CC,
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bool isTailCall, SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG);
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};
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}
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ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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setOperationAction(ISD::RET, MVT::Other, Custom);
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}
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std::pair<SDOperand, SDOperand>
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ARMTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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bool isVarArg, unsigned CC,
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bool isTailCall, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG) {
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assert(0 && "Not implemented");
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abort();
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}
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static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Copy;
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switch(Op.getNumOperands()) {
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default:
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assert(0 && "Do not know how to return this many arguments!");
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abort();
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case 1:
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return SDOperand(); // ret void is legal
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case 2:
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Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(1), SDOperand());
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break;
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}
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return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
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}
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SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default:
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assert(0 && "Should not custom lower this!");
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abort();
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case ISD::RET:
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return LowerRET(Op, DAG);
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}
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}
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// ARMDAGToDAGISel - ARM specific code to select ARM machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class ARMDAGToDAGISel : public SelectionDAGISel {
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ARMTargetLowering Lowering;
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public:
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ARMDAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(Lowering), Lowering(TM) {
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}
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void Select(SDOperand &Result, SDOperand Op);
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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// Include the pieces autogenerated from the target description.
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#include "ARMGenDAGISel.inc"
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};
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void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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CodeGenMap.clear();
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DAG.RemoveDeadNodes();
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ScheduleAndEmitDAG(DAG);
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}
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void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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SelectCode(Result, Op);
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}
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} // end anonymous namespace
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/// createARMISelDag - This pass converts a legalized DAG into a
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/// ARM-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createARMISelDag(TargetMachine &TM) {
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return new ARMDAGToDAGISel(TM);
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}
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