mirror of
https://github.com/c64scene-ar/llvm-6502.git
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be97e906e0
physical register numbers. This makes the hack used in LiveInterval official, and lets LiveInterval be oblivious of stack slots. The isPhysicalRegister() and isVirtualRegister() predicates don't know about this, so when a variable may contain a stack slot, isStackSlot() should always be tested first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123128 91177308-0d34-0410-b5e6-96231b3b80d8
244 lines
7.9 KiB
C++
244 lines
7.9 KiB
C++
//===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "spiller"
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#include "Spiller.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <set>
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using namespace llvm;
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namespace {
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enum SpillerName { trivial, standard, inline_ };
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}
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static cl::opt<SpillerName>
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spillerOpt("spiller",
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cl::desc("Spiller to use: (default: standard)"),
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cl::Prefix,
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cl::values(clEnumVal(trivial, "trivial spiller"),
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clEnumVal(standard, "default spiller"),
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clEnumValN(inline_, "inline", "inline spiller"),
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clEnumValEnd),
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cl::init(standard));
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// Spiller virtual destructor implementation.
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Spiller::~Spiller() {}
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namespace {
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/// Utility class for spillers.
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class SpillerBase : public Spiller {
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protected:
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MachineFunctionPass *pass;
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MachineFunction *mf;
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VirtRegMap *vrm;
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LiveIntervals *lis;
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MachineFrameInfo *mfi;
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MachineRegisterInfo *mri;
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const TargetInstrInfo *tii;
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const TargetRegisterInfo *tri;
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/// Construct a spiller base.
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SpillerBase(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
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: pass(&pass), mf(&mf), vrm(&vrm)
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{
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lis = &pass.getAnalysis<LiveIntervals>();
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mfi = mf.getFrameInfo();
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mri = &mf.getRegInfo();
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tii = mf.getTarget().getInstrInfo();
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tri = mf.getTarget().getRegisterInfo();
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}
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/// Add spill ranges for every use/def of the live interval, inserting loads
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/// immediately before each use, and stores after each def. No folding or
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/// remat is attempted.
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void trivialSpillEverywhere(LiveInterval *li,
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SmallVectorImpl<LiveInterval*> &newIntervals) {
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DEBUG(dbgs() << "Spilling everywhere " << *li << "\n");
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assert(li->weight != HUGE_VALF &&
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"Attempting to spill already spilled value.");
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assert(!TargetRegisterInfo::isStackSlot(li->reg) &&
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"Trying to spill a stack slot.");
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DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
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const TargetRegisterClass *trc = mri->getRegClass(li->reg);
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unsigned ss = vrm->assignVirt2StackSlot(li->reg);
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// Iterate over reg uses/defs.
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for (MachineRegisterInfo::reg_iterator
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regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
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// Grab the use/def instr.
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MachineInstr *mi = &*regItr;
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DEBUG(dbgs() << " Processing " << *mi);
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// Step regItr to the next use/def instr.
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do {
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++regItr;
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} while (regItr != mri->reg_end() && (&*regItr == mi));
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// Collect uses & defs for this instr.
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SmallVector<unsigned, 2> indices;
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bool hasUse = false;
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bool hasDef = false;
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for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
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MachineOperand &op = mi->getOperand(i);
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if (!op.isReg() || op.getReg() != li->reg)
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continue;
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hasUse |= mi->getOperand(i).isUse();
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hasDef |= mi->getOperand(i).isDef();
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indices.push_back(i);
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}
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// Create a new vreg & interval for this instr.
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unsigned newVReg = mri->createVirtualRegister(trc);
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vrm->grow();
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vrm->assignVirt2StackSlot(newVReg, ss);
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LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
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newLI->weight = HUGE_VALF;
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// Update the reg operands & kill flags.
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for (unsigned i = 0; i < indices.size(); ++i) {
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unsigned mopIdx = indices[i];
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MachineOperand &mop = mi->getOperand(mopIdx);
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mop.setReg(newVReg);
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if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
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mop.setIsKill(true);
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}
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}
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assert(hasUse || hasDef);
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// Insert reload if necessary.
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MachineBasicBlock::iterator miItr(mi);
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if (hasUse) {
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tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc,
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tri);
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MachineInstr *loadInstr(prior(miItr));
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SlotIndex loadIndex =
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lis->InsertMachineInstrInMaps(loadInstr).getDefIndex();
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vrm->addSpillSlotUse(ss, loadInstr);
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SlotIndex endIndex = loadIndex.getNextIndex();
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VNInfo *loadVNI =
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newLI->getNextValue(loadIndex, 0, lis->getVNInfoAllocator());
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newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI));
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}
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// Insert store if necessary.
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if (hasDef) {
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tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), newVReg,
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true, ss, trc, tri);
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MachineInstr *storeInstr(llvm::next(miItr));
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SlotIndex storeIndex =
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lis->InsertMachineInstrInMaps(storeInstr).getDefIndex();
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vrm->addSpillSlotUse(ss, storeInstr);
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SlotIndex beginIndex = storeIndex.getPrevIndex();
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VNInfo *storeVNI =
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newLI->getNextValue(beginIndex, 0, lis->getVNInfoAllocator());
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newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI));
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}
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newIntervals.push_back(newLI);
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}
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}
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};
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} // end anonymous namespace
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namespace {
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/// Spills any live range using the spill-everywhere method with no attempt at
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/// folding.
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class TrivialSpiller : public SpillerBase {
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public:
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TrivialSpiller(MachineFunctionPass &pass, MachineFunction &mf,
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VirtRegMap &vrm)
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: SpillerBase(pass, mf, vrm) {}
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void spill(LiveInterval *li,
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SmallVectorImpl<LiveInterval*> &newIntervals,
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const SmallVectorImpl<LiveInterval*> &) {
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// Ignore spillIs - we don't use it.
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trivialSpillEverywhere(li, newIntervals);
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}
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};
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} // end anonymous namespace
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namespace {
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/// Falls back on LiveIntervals::addIntervalsForSpills.
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class StandardSpiller : public Spiller {
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protected:
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MachineFunction *mf;
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LiveIntervals *lis;
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LiveStacks *lss;
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MachineLoopInfo *loopInfo;
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VirtRegMap *vrm;
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public:
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StandardSpiller(MachineFunctionPass &pass, MachineFunction &mf,
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VirtRegMap &vrm)
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: mf(&mf),
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lis(&pass.getAnalysis<LiveIntervals>()),
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lss(&pass.getAnalysis<LiveStacks>()),
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loopInfo(pass.getAnalysisIfAvailable<MachineLoopInfo>()),
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vrm(&vrm) {}
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/// Falls back on LiveIntervals::addIntervalsForSpills.
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void spill(LiveInterval *li,
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SmallVectorImpl<LiveInterval*> &newIntervals,
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const SmallVectorImpl<LiveInterval*> &spillIs) {
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std::vector<LiveInterval*> added =
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lis->addIntervalsForSpills(*li, spillIs, loopInfo, *vrm);
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newIntervals.insert(newIntervals.end(), added.begin(), added.end());
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// Update LiveStacks.
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int SS = vrm->getStackSlot(li->reg);
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if (SS == VirtRegMap::NO_STACK_SLOT)
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return;
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const TargetRegisterClass *RC = mf->getRegInfo().getRegClass(li->reg);
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LiveInterval &SI = lss->getOrCreateInterval(SS, RC);
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if (!SI.hasAtLeastOneValue())
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SI.getNextValue(SlotIndex(), 0, lss->getVNInfoAllocator());
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SI.MergeRangesInAsValue(*li, SI.getValNumInfo(0));
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}
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};
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} // end anonymous namespace
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llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
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MachineFunction &mf,
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VirtRegMap &vrm) {
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switch (spillerOpt) {
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default: assert(0 && "unknown spiller");
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case trivial: return new TrivialSpiller(pass, mf, vrm);
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case standard: return new StandardSpiller(pass, mf, vrm);
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case inline_: return createInlineSpiller(pass, mf, vrm);
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}
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}
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