llvm-6502/lib/Target/AArch64/AsmParser
Tim Northover 112102c7fe AArch64: disallow "fmov sD, #-0.0" during assembly.
We weren't checking the sign of the floating point immediate before translating
it to "fmov sD, wzr". Similarly for D-regs.

Technically "movi vD.2s, #0x80, lsl #24" would work most of the time, but it's
not a blessed alias (and I don't think it should be since people expect writing
sD to zero out the high lanes, and there's no dD equivalent). So an error it is.

rdar://20455398

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234372 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 22:49:47 +00:00
..
AArch64AsmParser.cpp AArch64: disallow "fmov sD, #-0.0" during assembly. 2015-04-07 22:49:47 +00:00
CMakeLists.txt AArch64/ARM64: move ARM64 into AArch64's place 2014-05-24 12:50:23 +00:00
LLVMBuild.txt AArch64/ARM64: move ARM64 into AArch64's place 2014-05-24 12:50:23 +00:00
Makefile AArch64/ARM64: move ARM64 into AArch64's place 2014-05-24 12:50:23 +00:00