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309 lines
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ReStructuredText
========
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TableGen
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========
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.. contents::
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:local:
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.. toctree::
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:hidden:
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BackEnds
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LangRef
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LangIntro
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Deficiencies
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Introduction
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============
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TableGen's purpose is to help a human develop and maintain records of
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domain-specific information. Because there may be a large number of these
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records, it is specifically designed to allow writing flexible descriptions and
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for common features of these records to be factored out. This reduces the
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amount of duplication in the description, reduces the chance of error, and makes
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it easier to structure domain specific information.
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The core part of TableGen parses a file, instantiates the declarations, and
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hands the result off to a domain-specific `backend`_ for processing.
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The current major users of TableGen are :doc:`../CodeGenerator`
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and the
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`Clang diagnostics and attributes <http://clang.llvm.org/docs/UsersManual.html#controlling-errors-and-warnings>`_.
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Note that if you work on TableGen much, and use emacs or vim, that you can find
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an emacs "TableGen mode" and a vim language file in the ``llvm/utils/emacs`` and
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``llvm/utils/vim`` directories of your LLVM distribution, respectively.
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.. _intro:
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The TableGen program
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====================
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TableGen files are interpreted by the TableGen program: `llvm-tblgen` available
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on your build directory under `bin`. It is not installed in the system (or where
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your sysroot is set to), since it has no use beyond LLVM's build process.
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Running TableGen
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----------------
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TableGen runs just like any other LLVM tool. The first (optional) argument
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specifies the file to read. If a filename is not specified, ``llvm-tblgen``
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reads from standard input.
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To be useful, one of the `backends`_ must be used. These backends are
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selectable on the command line (type '``llvm-tblgen -help``' for a list). For
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example, to get a list of all of the definitions that subclass a particular type
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(which can be useful for building up an enum list of these records), use the
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``-print-enums`` option:
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.. code-block:: bash
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$ llvm-tblgen X86.td -print-enums -class=Register
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AH, AL, AX, BH, BL, BP, BPL, BX, CH, CL, CX, DH, DI, DIL, DL, DX, EAX, EBP, EBX,
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ECX, EDI, EDX, EFLAGS, EIP, ESI, ESP, FP0, FP1, FP2, FP3, FP4, FP5, FP6, IP,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
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R11W, R12, R12B, R12D, R12W, R13, R13B, R13D, R13W, R14, R14B, R14D, R14W, R15,
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R15B, R15D, R15W, R8, R8B, R8D, R8W, R9, R9B, R9D, R9W, RAX, RBP, RBX, RCX, RDI,
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RDX, RIP, RSI, RSP, SI, SIL, SP, SPL, ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
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XMM0, XMM1, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, XMM2, XMM3, XMM4, XMM5,
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XMM6, XMM7, XMM8, XMM9,
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$ llvm-tblgen X86.td -print-enums -class=Instruction
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ABS_F, ABS_Fp32, ABS_Fp64, ABS_Fp80, ADC32mi, ADC32mi8, ADC32mr, ADC32ri,
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ADC32ri8, ADC32rm, ADC32rr, ADC64mi32, ADC64mi8, ADC64mr, ADC64ri32, ADC64ri8,
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ADC64rm, ADC64rr, ADD16mi, ADD16mi8, ADD16mr, ADD16ri, ADD16ri8, ADD16rm,
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ADD16rr, ADD32mi, ADD32mi8, ADD32mr, ADD32ri, ADD32ri8, ADD32rm, ADD32rr,
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ADD64mi32, ADD64mi8, ADD64mr, ADD64ri32, ...
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The default backend prints out all of the records.
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If you plan to use TableGen, you will most likely have to write a `backend`_
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that extracts the information specific to what you need and formats it in the
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appropriate way.
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Example
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-------
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With no other arguments, `llvm-tblgen` parses the specified file and prints out all
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of the classes, then all of the definitions. This is a good way to see what the
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various definitions expand to fully. Running this on the ``X86.td`` file prints
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this (at the time of this writing):
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.. code-block:: llvm
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...
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def ADD32rr { // Instruction X86Inst I
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string Namespace = "X86";
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dag OutOperandList = (outs GR32:$dst);
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dag InOperandList = (ins GR32:$src1, GR32:$src2);
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string AsmString = "add{l}\t{$src2, $dst|$dst, $src2}";
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list<dag> Pattern = [(set GR32:$dst, (add GR32:$src1, GR32:$src2))];
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list<Register> Uses = [];
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list<Register> Defs = [EFLAGS];
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list<Predicate> Predicates = [];
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int CodeSize = 3;
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int AddedComplexity = 0;
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bit isReturn = 0;
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bit isBranch = 0;
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bit isIndirectBranch = 0;
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bit isBarrier = 0;
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bit isCall = 0;
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bit canFoldAsLoad = 0;
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bit mayLoad = 0;
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bit mayStore = 0;
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bit isImplicitDef = 0;
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bit isConvertibleToThreeAddress = 1;
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bit isCommutable = 1;
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bit isTerminator = 0;
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bit isReMaterializable = 0;
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bit isPredicable = 0;
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bit hasDelaySlot = 0;
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bit usesCustomInserter = 0;
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bit hasCtrlDep = 0;
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bit isNotDuplicable = 0;
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bit hasSideEffects = 0;
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InstrItinClass Itinerary = NoItinerary;
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string Constraints = "";
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string DisableEncoding = "";
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bits<8> Opcode = { 0, 0, 0, 0, 0, 0, 0, 1 };
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Format Form = MRMDestReg;
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bits<6> FormBits = { 0, 0, 0, 0, 1, 1 };
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ImmType ImmT = NoImm;
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bits<3> ImmTypeBits = { 0, 0, 0 };
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bit hasOpSizePrefix = 0;
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bit hasAdSizePrefix = 0;
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bits<4> Prefix = { 0, 0, 0, 0 };
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bit hasREX_WPrefix = 0;
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FPFormat FPForm = ?;
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bits<3> FPFormBits = { 0, 0, 0 };
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}
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...
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This definition corresponds to the 32-bit register-register ``add`` instruction
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of the x86 architecture. ``def ADD32rr`` defines a record named
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``ADD32rr``, and the comment at the end of the line indicates the superclasses
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of the definition. The body of the record contains all of the data that
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TableGen assembled for the record, indicating that the instruction is part of
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the "X86" namespace, the pattern indicating how the instruction is selected by
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the code generator, that it is a two-address instruction, has a particular
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encoding, etc. The contents and semantics of the information in the record are
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specific to the needs of the X86 backend, and are only shown as an example.
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As you can see, a lot of information is needed for every instruction supported
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by the code generator, and specifying it all manually would be unmaintainable,
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prone to bugs, and tiring to do in the first place. Because we are using
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TableGen, all of the information was derived from the following definition:
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.. code-block:: llvm
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let Defs = [EFLAGS],
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isCommutable = 1, // X = ADD Y,Z --> X = ADD Z,Y
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isConvertibleToThreeAddress = 1 in // Can transform into LEA.
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def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
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(ins GR32:$src1, GR32:$src2),
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"add{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
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This definition makes use of the custom class ``I`` (extended from the custom
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class ``X86Inst``), which is defined in the X86-specific TableGen file, to
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factor out the common features that instructions of its class share. A key
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feature of TableGen is that it allows the end-user to define the abstractions
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they prefer to use when describing their information.
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Each ``def`` record has a special entry called "NAME". This is the name of the
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record ("``ADD32rr``" above). In the general case ``def`` names can be formed
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from various kinds of string processing expressions and ``NAME`` resolves to the
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final value obtained after resolving all of those expressions. The user may
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refer to ``NAME`` anywhere she desires to use the ultimate name of the ``def``.
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``NAME`` should not be defined anywhere else in user code to avoid conflicts.
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Syntax
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======
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TableGen has a syntax that is loosely based on C++ templates, with built-in
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types and specification. In addition, TableGen's syntax introduces some
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automation concepts like multiclass, foreach, let, etc.
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Basic concepts
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--------------
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TableGen files consist of two key parts: 'classes' and 'definitions', both of
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which are considered 'records'.
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**TableGen records** have a unique name, a list of values, and a list of
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superclasses. The list of values is the main data that TableGen builds for each
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record; it is this that holds the domain specific information for the
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application. The interpretation of this data is left to a specific `backend`_,
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but the structure and format rules are taken care of and are fixed by
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TableGen.
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**TableGen definitions** are the concrete form of 'records'. These generally do
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not have any undefined values, and are marked with the '``def``' keyword.
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.. code-block:: llvm
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def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
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"Enable ARMv8 FP">;
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In this example, FeatureFPARMv8 is ``SubtargetFeature`` record initialised
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with some values. The names of the classes are defined via the
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keyword `class` either on the same file or some other included. Most target
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TableGen files include the generic ones in ``include/llvm/Target``.
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**TableGen classes** are abstract records that are used to build and describe
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other records. These classes allow the end-user to build abstractions for
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either the domain they are targeting (such as "Register", "RegisterClass", and
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"Instruction" in the LLVM code generator) or for the implementor to help factor
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out common properties of records (such as "FPInst", which is used to represent
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floating point instructions in the X86 backend). TableGen keeps track of all of
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the classes that are used to build up a definition, so the backend can find all
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definitions of a particular class, such as "Instruction".
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.. code-block:: llvm
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class ProcNoItin<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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Here, the class ProcNoItin, receiving parameters `Name` of type `string` and
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a list of target features is specializing the class Processor by passing the
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arguments down as well as hard-coding NoItineraries.
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**TableGen multiclasses** are groups of abstract records that are instantiated
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all at once. Each instantiation can result in multiple TableGen definitions.
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If a multiclass inherits from another multiclass, the definitions in the
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sub-multiclass become part of the current multiclass, as if they were declared
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in the current multiclass.
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.. code-block:: llvm
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multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
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dag address, ValueType sty> {
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def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
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(!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
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Base, Offset, Extend)>;
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def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
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(!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset")
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Base, Offset, Extend)>;
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}
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defm : ro_signed_pats<"B", Rm, Base, Offset, Extend,
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!foreach(decls.pattern, address,
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!subst(SHIFT, imm_eq0, decls.pattern)),
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i8>;
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See the :doc:`TableGen Language Introduction <LangIntro>` for more generic
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information on the usage of the language, and the
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:doc:`TableGen Language Reference <LangRef>` for more in-depth description
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of the formal language specification.
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.. _backend:
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.. _backends:
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TableGen backends
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=================
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TableGen files have no real meaning without a back-end. The default operation
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of running ``llvm-tblgen`` is to print the information in a textual format, but
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that's only useful for debugging of the TableGen files themselves. The power
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in TableGen is, however, to interpret the source files into an internal
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representation that can be generated into anything you want.
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Current usage of TableGen is to create huge include files with tables that you
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can either include directly (if the output is in the language you're coding),
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or be used in pre-processing via macros surrounding the include of the file.
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Direct output can be used if the back-end already prints a table in C format
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or if the output is just a list of strings (for error and warning messages).
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Pre-processed output should be used if the same information needs to be used
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in different contexts (like Instruction names), so your back-end should print
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a meta-information list that can be shaped into different compile-time formats.
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See the `TableGen BackEnds <BackEnds.html>`_ for more information.
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TableGen Deficiencies
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=====================
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Despite being very generic, TableGen has some deficiencies that have been
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pointed out numerous times. The common theme is that, while TableGen allows
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you to build Domain-Specific-Languages, the final languages that you create
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lack the power of other DSLs, which in turn increase considerably the size
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and complexity of TableGen files.
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At the same time, TableGen allows you to create virtually any meaning of
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the basic concepts via custom-made back-ends, which can pervert the original
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design and make it very hard for newcomers to understand the evil TableGen
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file.
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There are some in favour of extending the semantics even more, but making sure
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back-ends adhere to strict rules. Others are suggesting we should move to less,
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more powerful DSLs designed with specific purposes, or even re-using existing
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DSLs.
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Either way, this is a discussion that will likely span across several years,
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if not decades. You can read more in the `TableGen Deficiencies <Deficiencies.html>`_
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document.
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