mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ca396e391e
The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203559 91177308-0d34-0410-b5e6-96231b3b80d8
99 lines
2.8 KiB
LLVM
99 lines
2.8 KiB
LLVM
; Test 64-bit compare and swap.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check CSG without a displacement.
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define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) {
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; CHECK-LABEL: f1:
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; CHECK: csg %r2, %r3, 0(%r4)
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; CHECK: br %r14
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%val = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst seq_cst
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ret i64 %val
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}
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; Check the high end of the aligned CSG range.
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define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: csg %r2, %r3, 524280(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65535
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%val = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
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ret i64 %val
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: agfi %r4, 524288
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; CHECK: csg %r2, %r3, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65536
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%val = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
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ret i64 %val
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}
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; Check the high end of the negative aligned CSG range.
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define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) {
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; CHECK-LABEL: f4:
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; CHECK: csg %r2, %r3, -8(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -1
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%val = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
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ret i64 %val
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}
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; Check the low end of the CSG range.
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define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: csg %r2, %r3, -524288(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65536
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%val = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
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ret i64 %val
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}
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; Check the next doubleword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r4, -524296
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; CHECK: csg %r2, %r3, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65537
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%val = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
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ret i64 %val
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}
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; Check that CSG does not allow an index.
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define i64 @f7(i64 %cmp, i64 %swap, i64 %src, i64 %index) {
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; CHECK-LABEL: f7:
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; CHECK: agr %r4, %r5
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; CHECK: csg %r2, %r3, 0(%r4)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%ptr = inttoptr i64 %add1 to i64 *
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%val = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
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ret i64 %val
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}
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; Check that a constant %cmp value is loaded into a register first.
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define i64 @f8(i64 %dummy, i64 %swap, i64 *%ptr) {
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; CHECK-LABEL: f8:
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; CHECK: lghi %r2, 1001
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; CHECK: csg %r2, %r3, 0(%r4)
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; CHECK: br %r14
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%val = cmpxchg i64 *%ptr, i64 1001, i64 %swap seq_cst seq_cst
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ret i64 %val
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}
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; Check that a constant %swap value is loaded into a register first.
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define i64 @f9(i64 %cmp, i64 *%ptr) {
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; CHECK-LABEL: f9:
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; CHECK: lghi [[SWAP:%r[0-9]+]], 1002
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; CHECK: csg %r2, [[SWAP]], 0(%r3)
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; CHECK: br %r14
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%val = cmpxchg i64 *%ptr, i64 %cmp, i64 1002 seq_cst seq_cst
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ret i64 %val
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}
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